Ratnesh Samaiya — Software Engineer
ownership for block level integration activities RTL2GDS for cpu blocks 3nm, 5nm, 7nm, 12nm finfet node Synthesis, floorplanning , place and route, clock, cts Block Level STA (Pre-layout and Post Layout) Timing closure ,Timing ECO power analysis Ptpx Design Compiler, Genus, innovus Prime-Time, Tweaker
Stackforce AI infers this person is a VLSI design expert with a focus on physical design and power optimization.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 9 mos
Skills
- Physical Design
- Static Timing Analysis
- Power Optimization
- Clock Tree Distribution
Career Highlights
- Expert in custom CPU RTL2GDS signoff processes.
- Proficient in power optimization and static timing analysis.
- Experienced in advanced node technologies including 3nm and 5nm.
Work Experience
Qualcomm
Staff Engineer (1 yr 6 mos)
Sr lead (1 yr 11 mos)
sr engineer (2 yrs 10 mos)
MediaTek
Sr Engineer (6 mos)
Engineer (1 yr 8 mos)
Tessolve Semiconductor PVT LTD (TessolveDTS Inc)
Engineer (1 yr 6 mos)
Indian Institute of Information Technology, Allahabad, India
Teaching Assistant (1 yr 10 mos)
Education
Master’s Degree at Indian Institute of Information Technology Allahabad
Bachelor of Engineering (B.E.) at SHRI RAM INSTITUTE OF TECHNOLOGY, JABALPUR
