Jan 2019 – Feb 2020 · 1 yr 1 mo · Chandler, Arizona

• Designed test plans for validating Intel’s sort and class testers and its software.
• Worked closely on optimizing the PatGen and DPS area of the testers to make them bug free and user friendly. Delivered easy to deploy solution for OS imaging on tester farms.

Oct 2018 – Jan 2019 · 3 mos · Greater New York City Area

• Led the product development and design of a holographic AI assistant competing with the likes of the technology behind Amazon's Alexa & Google's Assistant.
• Deliberated cost analysis with manufacturers and suppliers from around the world for each component involved in the design. Performed a detailed market study, developed a 3D model of the product and drafted a final Bill-of-Materials speculating the costs covering PCB components, purchased and fabricated parts, packaging, shipping and manual assembly costs.
• Have been able to make most of my startup experience by having productive brainstorming discussions with the founder and analyzed various view points of a consumer in contrast with the business, financial and technological stand point of the company.

Sep 2017 – Dec 2017 · 3 mos · Evanston, IL

• Teaching assistant for courses ASIC and FPGA Design (EECS-355) & Introduction to Computer Engineering (EECS-203).

Mar 2017 – Jun 2018 · 1 yr 3 mos · Evanston, IL

• Working under Prof. Russ Joseph in Low power architecture lab on Reconfigurable hardware accelerators as my thesis work.

Jun 2017 – Sep 2017 · 3 mos · San Francisco Bay Area

• Established workload power characterization at lowest kernel level for DL workloads enabling platform generalization & projections for other architectures.
• Instrumented industry leading GPUs & FPGAs for the measurement of power and performance, which was the key to develop suitable power models.

Jun 2015 – Oct 2015 · 4 mos · Mumbai Area, India

• Designed module (including the PCB layout design) to track objects in real-time.
• Project selected as top 10 in an idea submission contest among 159 participants from around the world.

Oct 2014 – May 2016 · 1 yr 7 mos · SRM University

• Secured 1st rank in the Critical Design Review (CDR) Presentation Stage in CANSAT 2015.
• Designed the electronics of Payload and the Container of the CANSAT among the constraints of power consumption and weight limitations.

May 2014 – Jul 2014 · 2 mos · Hyderabad Area, India

• Studied and practically experienced the manufacturing, over-hauling and simulation of the Radar System incorporated in the India's most advanced third generation multi-combat role fighter Sukhoi-30 MKI.
• Drafted a detailed report on the topics of Mechanics of Flight, Su-30 MKI's profile, Radar principles, Characteristics and different operational modes of the Radar used in Su-30, Testing and Assembly operations.

Apr 2013 – Apr 2015 · 2 yrs · SRM University, Chennai

• Bagged the "Best Economical Robot" award at the Robocon-2014.
• Managed the finances amounting to Rs. 1.2 million as well as the logistics of the 30 member team.
• Innovating for solving the problem statement utilizing optimal resources.