Sudeepthi Manepalli

Software Engineer

Tanuku, Andhra Pradesh, India4 yrs 11 mos experience
Highly Stable

Key Highlights

  • 4 years of experience in Physical Design Engineering.
  • Expert in optimizing chip layout for performance and power.
  • Proficient in industry-standard tools like Fusion Compiler and Innovus.
Stackforce AI infers this person is a Physical Design Engineer specializing in semiconductor design and optimization.

Contact

LinkedIn

Skills

Core Skills

Physical DesignPlace And Route (pnr)

Other Skills

PNRTCLScriptingC (Programming Language)Python (Programming Language)Static Timing AnalysisPerlDigital ElectronicsMicrocontrollersC++VerilogVHDLMicroprocessorsComputer Architecture

About

Experienced Physical Design Engineer specializing in floorplanning and Place and Route (PnR) with 4 years of industry experience. Proficient in optimizing chip layout for performance, power, and area considerations. Skilled in utilizing industry-standard tools like Fusion Compiler and Innovus etc. to achieve design goals efficiently. Experience in handling Netlist to GDS convergence in 5/4/3nm.

Experience

4 yrs 11 mos
Total Experience
3 yrs 9 mos
Average Tenure
1 yr 2 mos
Current Experience

Amd

Senior Silicon Design Engineer

Mar 2025 – Present · 1 yr 2 mos · Hyderabad

Qualcomm

3 roles

Senior Engineer

Promoted

Nov 2024 – Mar 2025 · 4 mos

Engineer

Promoted

Nov 2022 – Nov 2024 · 2 yrs

PNRTCLPhysical DesignPlace and Route (PnR)

Associate Engineer

Jun 2021 – Nov 2022 · 1 yr 5 mos

PNRTCLPhysical DesignPlace and Route (PnR)

Education

National Institute of Technology Calicut

Bachelor of Technology — EEE

Jan 2017 – Jan 2021

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