Jan 2023 – Aug 2025 · 2 yrs 7 mos · Noida, Uttar Pradesh, India · On-site

• RTL2GDS Implementation, Automation Lead - Chip Design Team.

Feb 2021 – Dec 2022 · 1 yr 10 mos · Bengaluru, Karnataka, India · On-site

• I am a part of BigCore Layout team as a PDE.
• Worked on layout convergence of Hierarchical
• Data path (DP) and Register Files (RF) Designs including Block level floor planning, placement, Semi automatic routing, Physical Verification such as DRC and LVS, Reliability Verification( IR & EM checks ),
• Parasitic extraction, Pre and Post Routing Static Timing Analysis (STA). Also Worked on various scripts on ICC2, Innovus, Primetime using TCL/TK , Bash scripting.

Jul 2020 – Oct 2020 · 3 mos · Noida, Uttar Pradesh, India

• Physical Design Intern.
• ■■ Unix/Linux: ->
• ● Manipulation in file through different Vi Editor, SED & AWK command.
• ■■ Automation in TCL:
• ● Created a script that will get the count types of particular Vt, drive strengths, cell types,
• comb & sequential cells from a given Verilog netlist.
• ● Created a script to create csv file which has the first column will be victim net, the second
• column will be the top 2 aggressor net name and the third column will be total slack.
• ● Created a script for a two different tech standard cell library, get the characteristics of each
• cell in the library such as delay, max_cap, transition, area, input/output pins count, leakage
• power, and created a comparison summary for user input cell.
• ■■ Verilog HDL: ->
• ● Simulation of different Verilog codes including MUX design with delay constraints, shift
• registers, flip flops, etc using different modeling and user-defined primitives.
• Tool used - Modelsim.
• ■■ Synthesis: ->
• ● Overview of USB Protocol, Synthesis Fundamentals, Methodology development using Yosys tool guide, Synthesis Flow Flush on USB Protocol, Synthesis of USB with and without constraints, and Calculation of Total Design Area using multiple TCL scripts.
• Tool used - Yosys.
• ■■ Physical Design: ->
• ● Physical Design Concepts.
• ● Placement of USB IP netlist using 180nm std cell library, performed placement with different Floorplan variation and compared with normal netlist placement results.
• Tool used - Graywolf.

Jul 2019 – Jul 2020 · 1 yr · Noida Area, India

• Foundation Of VLSI DESIGN Course.
• Linux/Unix & Scripting (TCL,PERL,Python) (Project on Automation using TCL like Data Extraction of user input cell from .lib file, etc), TCL Scripts for Cell delay Calculation (STA).
• Advanced Digital Electronics Fundamentals and Simulation of different circuits using Verilog Hardware Language using Modelsim.
• Fundamentals of Electronics,Circuit theory,Device Physics,Semiconductor Physics, Analog Electronics, CMOS and Advanced Electronics Concepts.
• CMOS Fabrication and VLSI Technology.
• Standard Cells Layout Design.(Project on 90nm tech node using Cadence Virtuoso).
• Fundamentals of Logic Synthesis,Static Timing Analysis, Parasitic Extraction. (Project on Standard circuit Delay Calculation using OpenSTA Tool).
• Deep Understanding of Physical Design Flow and ASIC Design Flow.(Project on study of various files used at different stages of ASIC Design Flow).

Jan 2019 – Feb 2019 · 1 mo · Kolkata Area, India

• Intern (CNS) DEPARTMENT || Intern Completion Certificate
• Training was focussed on various Aeronautical Communications, Navigation and Surveillance Facilities.

Feb 2018 – Apr 2018 · 2 mos · Greater noida

• Stage 2 Finalist || Participation Certificate.
• I made this Project with the help of "Arduino" for the Smart India Hackathon - Hardware Edition 2018.
• About Project - Automatic Traffic Indication System with modified version of Indian Traffic System.