Venkatesh Subramanian

Software Engineer

Bengaluru, Karnataka, India30 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC design and implementation.
  • Led successful tape outs for early IoT ASICs.
  • Mentored engineers in advanced design methodologies.
Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in ASIC and IoT solutions.

Contact

Skills

Other Skills

SoCASICVerilogVLSIRTL designDebuggingSemiconductorsStatic Timing AnalysisICEDASystemVerilogFPGALogic DesignEmbedded SystemsPerl

About

PASSION: To play a key role in conceptualizing, architecting & implementing designs; use my leadership skills in guiding, mentoring teams; to create innovative IOT solutions that make life simple. SKILLS AND ACCOMPLISHMENTS: A successful career with deep domain expertise spanning X86, mobile apps processor, Communication SoCs and Peripheral IPs & chips and embedded systems; covering the entire length and depth of ASIC design cycle from System level logic partitioning, micro-architecture, RTL coding, simulation and synthesis. Part of the rise of ASIC/RTL design in India in the 90s and later in 2000s. Successfully taped out early-IOT ASICs/FPGAs for industrial applications TECHNICAL LEADERSHIP: Led teams to successful tape outs and IP delivery and silicon debug, Led SoC teams, test-plans reviews for DV and power management, Led PD/Layout discussion and timing closure runs, Led the design of S/W applications, use-cases, device drivers, etc. Shaped customer use-cases, specs, suggested features/functions, etc. Mentored many engineers, guided them, created methodologies

Experience

30 yrs 4 mos
Total Experience
2 yrs 6 mos
Average Tenure
3 yrs 2 mos
Current Experience

Sima.ai

Senior Principal Engineer

Mar 2023Present · 3 yrs 2 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

Front End Lead

Nov 2019Feb 2023 · 3 yrs 3 mos · Bangaon, West Bengal, India

Maxim integrated

Principal MTS

Oct 2017Jul 2019 · 1 yr 9 mos

  • This role involves being a strong hands-on Technical lead, grow and manage a team of Digital FE engineers. Manage, Lead and execute multiple mixed-signal design chips from spec to tapeout.

Eximius design

Distinguished Engineer

Mar 2016Sep 2017 · 1 yr 6 mos · Bengaluru, Karnataka, India

Amd

Senior Member of Technical Staff

Jul 2013Oct 2015 · 2 yrs 3 mos

  • Front End RTL lead, X86, L2 Cache

Broadcom india research pvt. ltd.

Principal Engineer

Feb 2007Jul 2013 · 6 yrs 5 mos · Bangalore

  • RTL and Logic Design

Texas instruments

Lead Engineer - Verification

Jan 2003Jan 2006 · 3 yrs

Texas instruments india

Lead Engineer

Jan 2003Jan 2006 · 3 yrs

Alcatel

Electrical Engineer III

Jul 2002Nov 2003 · 1 yr 4 mos

Cachevision inc

ASIC Design Engineer

Jan 2001Jan 2002 · 1 yr · San Jose, CA

Vibha

Executive Lead Bayarea Action Center

Jan 2001Dec 2001 · 11 mos

  • As a Volunteer

Sigma designs

ASIC Design Engineer

Jan 2000Jan 2001 · 1 yr

Eclipse international

ASIC Design Engineer

May 1997Nov 1999 · 2 yrs 6 mos · Mountain View, CA

Center for development of telematics, delhi

Research Engineer

Jan 1993Jan 1997 · 4 yrs

Education

Pondicherry Engineering College

B.Tech — Electronics and Communications Engineering

Jan 1989Jan 1993

Kendriya Vidyalaya

High School

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