I

Ishdeep Singh

Software Engineer

Noida, Uttar Pradesh, India16 yrs 4 mos experience
Highly Stable

Key Highlights

  • Expert in System Verilog based verification environments.
  • Extensive experience in PCIe, Ethernet, and AXI protocols.
  • Proven track record in automotive SOC verification.
Stackforce AI infers this person is a Verification Engineer specializing in semiconductor and networking industries.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationSystem Verilog

Other Skills

VerificationTestbench DevelopmentPCIeEthernetOVMSoCASICVerilogSimulationsPerl

About

Verification engineer with experience developing and utilizing System Verilog based verification environments (VMM ,UVM, OVM). Domain expertise included PCIe, Ethernet, AXI, JTAG Programming/Language Skills Include: • System Verilog (UVM/OVM) • Debugged RTL using simulators like Questasim, IUS/Simvision, and Synopsys VCS.

Experience

16 yrs 4 mos
Total Experience
3 yrs 7 mos
Average Tenure
1 yr 9 mos
Current Experience

Renesas electronics

Principal Engineer

Jul 2024 – Present · 1 yr 9 mos · Noida, Uttar Pradesh, India · On-site

Nxp semiconductors

3 roles

Senior Principal Engineer

Apr 2023 – Jul 2024 · 1 yr 3 mos

Principal Engineer

Promoted

Jul 2020 – Mar 2023 · 2 yrs 8 mos

Staff Design Engineer

May 2017 – Jul 2020 · 3 yrs 2 mos

  • Part of a Team responsible for Automotive SOC verification

Paradigm works

Consulting Engineer

Nov 2012 – May 2017 · 4 yrs 6 mos · Home

  • Worked as a consulting Engineer with various clients for verification of chips from Networking ,Processor and Aviation Industry .
  • Worked on Verifying IP's at block level using SV based testbench and at SoC level using C based testbench.
  • Worked on Various System verilog Based methodologies like VMM ,OVM and UVM
  • Worked on various interface protocols Like PCIe2.0 ,PCIe 3.0 , Ethernet
  • Planned and executed verification testplans
  • Co ordinate and Interfacing with various team .
System VerilogVerificationTestbench DevelopmentPCIeEthernetFunctional Verification

Mentor graphics

Senior Member of Technical Staff

Apr 2012 – Oct 2012 · 6 mos · Noida

  • Worked in the VIP team

Appliedmicro

2 roles

Senior Hardware Verification Engineer

Promoted

Jun 2011 – Mar 2012 · 9 mos

  • Worked on Verifying IP's at block level and SoC level using system verilog and OVM
  • Worked on various protocols like Ethernet , Axi
System VerilogOVMVerificationFunctional Verification

Hardware Verification Engineer

Aug 2009 – May 2011 · 1 yr 9 mos

  • Worked on Verifying IP's at block level and SoC level using system verilog and OVM
  • Worked on various protocols like Ethernet , Axi
System VerilogOVMVerificationFunctional Verification

Education

Indian Institute of Technology, Kanpur

BTech + MTech (Dual Degree) — Electical Engineering

Jan 2004 – Jan 2009

DPS RK Puram

Jan 2001 – Jan 2003

Sherwood College ,Nainital

Jan 1992 – Jan 2001

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