Krishnamachary Prathapuram — Director of Engineering
- Demonstrated over 25+ years of comprehensive expertise in diverse ASIC/SOC domains including Physical Design, STA, DFT, Design, and Verification. - Led and managed a high-performing team of 40+ Engineers, fostering collaboration and achieving project milestones. - Engaged in the successful Tapeout/Execution of 40+ SOC/ASIC projects spanning technology nodes from 180nm to cutting-edge 3nm. - Specialised in steering complex chip Physical Design activities, ensuring precision and optimal outcomes. - Proficiency in developing and implementing Timing Constraints for various modes, executing STA planning, and achieving Sign-Off for intricate SOCs, handling complexities in clocks, modes, Timing corners, and size. - Extensive experience in overseeing full SOC/ASIC projects, displaying in-depth understanding and execution of Fullchip Floorplan/Bus/Feedthru, STA Planning/Execution/Sign-off, Physical Design Closure of Critical Blocks, DFT Architecture, and Constraints Development for STA, IR/EM Analysis using RHSC, Post Silicon ATPG debug, Formal verification, Block Design, and Verification. - Successfully led Fullchip timing closure for more than 20 ASIC/SOCs comprising 200+ million gate SOCs. - Pioneered the development of methodologies, automation tools, and productivity enhancement techniques, ensuring efficient project execution and progress tracking.
Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in ASIC/SOC design and verification.
Location: Bengaluru, Karnataka, India
Experience: 24 yrs 9 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Over 25 years of expertise in ASIC/SOC domains.
- Led a team of 40+ engineers to achieve project milestones.
- Successfully executed 40+ SOC/ASIC projects across various technology nodes.
Work Experience
Juniper Networks
ASIC Director (3 yrs 10 mos)
ASIC Senior Manager (4 yrs 11 mos)
ASIC Staff Engineer (1 yr 11 mos)
ASIC Engineer -4 (2 yrs 7 mos)
AMD
Member Technical Staff ( Chip Lead) (3 yrs 11 mos)
Kpit Cummins Infosystsms Limited
Project Lead (1 yr 8 mos)
Conexant Systems
Sr.Member Technical Staff (2 yrs 5 mos)
Nevis Networks Inc
ASIC Design Engineer (8 mos)
HCL Technologies
ASIC Design Engineer (9 mos)
Telecruz Technologies
ASIC Design Engineer (1 yr)
ISRO , LEOS Bangalore
Project Trainee (1 yr)
Education
M.Sc.Tech at National Institute of Technology Warangal
Bachelor of Science at Kakatiya University