Krishnamachary Prathapuram

Director of Engineering

Bengaluru, Karnataka, India24 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 25 years of expertise in ASIC/SOC domains.
  • Led a team of 40+ engineers to achieve project milestones.
  • Successfully executed 40+ SOC/ASIC projects across various technology nodes.
Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in ASIC/SOC design and verification.

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Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Timing ClosureVHDLVerilogSpyglass Predictive AnalyzerSynthesisClock Tree SynthesisFloorplanningPNRConformal LECPrimeTimeSINanoTimeGood understanding of Physical Verification (LVS, DRC) Sign-offIR DropC++Perl

About

- Demonstrated over 25+ years of comprehensive expertise in diverse ASIC/SOC domains including Physical Design, STA, DFT, Design, and Verification. - Led and managed a high-performing team of 40+ Engineers, fostering collaboration and achieving project milestones. - Engaged in the successful Tapeout/Execution of 40+ SOC/ASIC projects spanning technology nodes from 180nm to cutting-edge 3nm. - Specialised in steering complex chip Physical Design activities, ensuring precision and optimal outcomes. - Proficiency in developing and implementing Timing Constraints for various modes, executing STA planning, and achieving Sign-Off for intricate SOCs, handling complexities in clocks, modes, Timing corners, and size. - Extensive experience in overseeing full SOC/ASIC projects, displaying in-depth understanding and execution of Fullchip Floorplan/Bus/Feedthru, STA Planning/Execution/Sign-off, Physical Design Closure of Critical Blocks, DFT Architecture, and Constraints Development for STA, IR/EM Analysis using RHSC, Post Silicon ATPG debug, Formal verification, Block Design, and Verification. - Successfully led Fullchip timing closure for more than 20 ASIC/SOCs comprising 200+ million gate SOCs. - Pioneered the development of methodologies, automation tools, and productivity enhancement techniques, ensuring efficient project execution and progress tracking.

Experience

24 yrs 9 mos
Total Experience
3 yrs 1 mo
Average Tenure
13 yrs 3 mos
Current Experience

Juniper networks

4 roles

ASIC Director

Promoted

Jul 2022Present · 3 yrs 10 mos

ASIC Senior Manager

Promoted

Jul 2017Jun 2022 · 4 yrs 11 mos

ASIC Staff Engineer

Jul 2015Jun 2017 · 1 yr 11 mos

ASIC Engineer -4

Nov 2012Jun 2015 · 2 yrs 7 mos

Amd

Member Technical Staff ( Chip Lead)

Dec 2008Nov 2012 · 3 yrs 11 mos · Hyderabad, Telangana, India

  • As a Staff Engineer at AMD , Worked as the PD manager for my most recent projects . Taped out 6 chips of very high complexity in size and clock structure and frequency as Static Timing Analysis Lead . Three of them are on TSMC 45nm and rest three are on 28nm nodes .

Kpit cummins infosystsms limited

Project Lead

Mar 2007Nov 2008 · 1 yr 8 mos · Bangalore Urban, Karnataka, India

Conexant systems

Sr.Member Technical Staff

Oct 2004Mar 2007 · 2 yrs 5 mos

Nevis networks inc

ASIC Design Engineer

Feb 2004Oct 2004 · 8 mos

Hcl technologies

ASIC Design Engineer

May 2003Feb 2004 · 9 mos

Telecruz technologies

ASIC Design Engineer

Jan 2002Jan 2003 · 1 yr

Isro , leos bangalore

Project Trainee

Jan 2000Jan 2001 · 1 yr · Bangalore

Education

National Institute of Technology Warangal

M.Sc.Tech — Engineering Physics with Specialization in Photonics(Electronics & Optical communications)

Jan 1998Jan 2001

Kakatiya University

Bachelor of Science — Instrumentation

Jan 1995Jan 1998

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