Bhavesh Gopani — DevOps Engineer

Results-driven ASIC DFT Engineer with 6 years of industrial experience and a proven track record of leading teams to success. Specializing in Design for Test (DFT) methodologies, I have successfully contributed to the silicon bring-up of over 7+ System-on-Chip (SoC) projects across a wide range of technology nodes from 110 nm to 3 nm. Proficient in utilizing cutting-edge DFT tools such as Synopsys and Mentor Graphics, I excel in scan insertion and ATPG techniques, including advanced fault models like SSA, TR, Path Delay, SDD, IDDQ, and RSQ. With a focus on complex, multi-million gate designs and hierarchical architectures, I have achieved compression ratios exceeding 1000x. Experienced in improving test coverage through various techniques and supporting post-silicon validation for multiple SoCs under different fault models. I possess a strong understanding of MBIST insertion using Mentor Tessent MBIST and am knowledgeable in the latest standards including IEEE 1687 (iJTAG) and IEEE 1500 for IP pattern generation and validation. Additionally, I have experience in pattern verification with and without timing constraints, along with a foundational understanding of Physical Design/STA and RTL synthesis.

Stackforce AI infers this person is a DFT Engineer specializing in ASIC design and validation within the semiconductor industry.

Experience: 14 yrs 7 mos