Akshay Khandelwal

Software Engineer

Gurugram, Haryana, India7 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expertise in RTL and physical design for leading semiconductor companies.
  • Proven track record in formal verification and digital design.
  • Strong educational background from IIT Kanpur in Electrical Engineering.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and formal verification.

Contact

LinkedIn

Skills

Other Skills

RTL DesignPhysical DesignVerilogProgrammingResearchProject ManagementData AnalysisEngineeringDesignAnalytical SkillsSemiconductorsCircuit DesignCPython (Programming Language)C++

About

Education: Bachelors' and Masters' in Electrical Engineering, IIT Kanpur. Experience: - Digital Design Engineer at Intel, Bangalore , India. - Experience in both physical design and RTL design.

Experience

7 yrs 10 mos
Total Experience
3 yrs 11 mos
Average Tenure
3 yrs 11 mos
Current Experience

Nvidia

Senior Formal Verification Engineer

Jun 2022 – Present · 3 yrs 11 mos · Gurugram, Haryana, India

Intel corporation

2 roles

Formal Verification Engineer

Dec 2019 – Jun 2022 · 2 yrs 6 mos

  • Developing formal proof for Memory Interface Unit in execution cluster.

Digital Design Engineer

Jul 2018 – Dec 2019 · 1 yr 5 mos

  • Working on RTL design for memory cluster of Intel Core Processors
  • Worked on physical design synthesis for memory cluster. Responsible for overall back-end convergence of the digital design including functionality, timing, power and quality.

National highway authority of india

Research Intern

May 2016 – Jul 2016 · 2 mos · Jaipur, Rajasthan, India

  • - worked on implementation of automatic toll collection (FasTag).

Education

Indian Institute of Technology, Kanpur

Master's degree — Electrical Engineering

Jan 2017 – Jan 2018

Indian Institute of Technology, Kanpur

Bachelor's degree — Electrical Engineering

Jan 2013 – Jan 2017

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