Mohnesh Yalavarthi

Product Engineer

Bengaluru, Karnataka, India3 yrs 11 mos experience

Most Likely To Switch

Key Highlights

Expertise in ASIC flow and Physical Design.
Proficient in Static Timing Analysis and DRC verification.
Strong communication and interpersonal skills.

Stackforce AI infers this person is a VLSI Physical Design Engineer with expertise in ASIC and timing analysis.

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Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

ASIC flowAPR flowpowerplanningplacementFloorplanningctsLayout Versus Schematic (LVS)RoutingDesign Rule Checking (DRC)

About

A Motivated Physical Design Engineer with In-depth Knowledge of ASIC flow, Physical design, and Static Timing analysis (STA). Performed APR Block Level Implementation (Floorplanning, Power planning, Placement, CTS, Routing) on 3nm to 40nm Technology node and verified for DRC, LVS, and Antenna issues. The tools used for APR flow implementation is Innovus, Genus, Voltus and the Tool used for verifying timing analysis is Tempus. I believe I am an efficient communicator with strong Interpersonal skills which helps me adapt to a team. I can also assure that I provide with the best professional outcome.

Experience

3 yrs 11 mos

Total Experience

1 yr 3 mos

Average Tenure

1 yr 8 mos

Current Experience

Cadence design systems

Design Engineer AE

Sep 2024 – Present · 1 yr 8 mos · Bengaluru, Karnataka, India

Mediatek

Synthesis and STA Engineer

Jan 2023 – Sep 2024 · 1 yr 8 mos · Bengaluru, Karnataka, India

Rv-vlsi vlsi and embedded systems design center

Physical Design Trainee

Apr 2022 – Oct 2022 · 6 mos · Bengaluru, Karnataka, India

I have been awarded a Time To Productivity (TTP) of 2 for my LIVE PROJECT worked at RV-VLSI - AUTOMATIC PLACE AND ROUTE OF AN SOC BLOCK.
 Technology: 40nm, Macro Count: 34, Standard cell count: 38403, Supply voltage: 1.1V, Power Budget: 600mW, Clock
frequency: 833MHz, IR drop: (VDD+VSS): 5%.
 Designing a Floorplan by determining macro placement as per dataflow diagram, and fly lines, and using the macro guidelines
in order to achieve contiguous core area and good utilization.
 Building a Power plan to maintain power network connectivity and IR drop. Also ensuring that there were no missing vias,
floating wires, or power-ground DRC violations.
 Creating a placement block by inserting pre-placement cells, placement constraints, and sufficient spacings in order to control
the congestion and DRC violations obtained.
 Performing clock tree synthesis and optimization using classic, CCD flows and analyzing the tool's behavior by comparing
the timing reports in both flows.
 Rectifying the LVS errors like shorts which were obtained post-routing by removing the overlapped routes and doing
manual routing wherever necessary.
 Analyzing and resolving the antenna violations by inserting the metal jumper and the diode into the layout.
 Understanding the timing reports at every stage of PD flow, finding the cause of timing violations, and how some of the
violated paths are being reduced in later stages

ASIC flowAPR flowpowerplanningplacementFloorplanningcts+5

Cognizant

Programmer Analyst Trainee

Aug 2021 – Mar 2022 · 7 mos · Bangalore Urban, Karnataka, India

Worked as a Programmer Analyst Trainee and was assigned in Business Intelligence Domain as a Developer.
Trained on Data Visualization tools like Tableau, PowerBI, Qlikview, Qliksense and have created Reports using Data Analytics and Data Visualization tools.
Later was allocated in Crystal Reports Project where I got experience on tools like Visual studio professional edition, Foxpro, crystal reports for visual studio and SQL management studio. As a developer I have developed Reports using visual studio (dotnet code included) and verified these reports using FoxPro application.

Iit guwahati

Intern

Jul 2020 – Sep 2020 · 2 mos

Digital Domain in Very Large-Scale Integration (VLSI) Field
Performed few basics Verilog Coding using VIVADO Software and ModelSim Software .
Gone through various modeling in Verilog such as Behavioral Level Modeling, Gate Level Modeling and Data flow level Modeling.

Verzeo

Student Intern

Jun 2020 – Sep 2020 · 3 mos · Bangalore Urban, Karnataka, India

Successfully completed an Internship Program 'Machine Learning with Python' from Verzeo Company, Bangalore in association with IIT Kharagpur.
Well versed in Machine Learning Algorithms and used various algorithms on different datasets and performed various data operations using python Jupyter notebook.
have performed EDA and Data Analytics to find the accuracies on various datasets.

Vi solutions, bangalore

Intern

May 2020 – Jun 2020 · 1 mo · Bangalore Urban, Karnataka, India

Successfully worked as an Intern at VI Solutions, Bangalore.
Performed Simulations using LABVIEW Software
Focused on LABVIEW applications on Internet of Things Platform(IOT) which includes ‘Image Processing to Detect Patterns in Video'