May 2014 – Oct 2024 · 10 yrs 5 mos · Bengaluru, Karnataka, India

• Managing Teams (50+ Engineers) for Physical Design, Timing (STA)& Power Integrity (PI)
• 30+ project Tape Outs (including low power designs) in various technology nodes (40nm/28nm/22nm/16nm/14nm/12nm/10nm/7nm/6nm/4nm) for different markets segments like Connectivity, Smart Phones, Modems, Networking, Home Entertainment and Automobiles.
• Built high performing teams from scratch – hiring/training/mentoring/execution/project delivery.
• Netlist to GSDII implementation of Projects including Partitioning, Floorplanning, Placement, CTS, Routing, Timing Closure (STA) and Signoff (PV + PI)
• Managing PI Signoff team to undertake PI Tasks like Power Mesh Creation, co-design & IR Analysis (Static & Dynamic) closely working with the global PD, co-design, designers & Packaging teams.
• Cross site collaboration with teams from Taiwan, China, and Singapore for Project Delivery/Execution.
• Worked with Contracting Partners for resourcing of Project as per need and maintained matrix for contractor quality to improve productivity.
• Front Ending with EDA partners to push the PPAS envelope for projects by identifying areas of improvement and driving new methodology for next generation projects.
• Part of the core team that setup the operations of the Mediatek in Bangalore and helped to grow various teams in the organization.
• As a part of the Bangalore center setup, worked with support teams like IT & HR to enable processes and policies as per global company policies and existing industry best practices.

Apr 2013 – Apr 2014 · 1 yr · Bengaluru, Karnataka, India

• Managing (100+ Engineers) of IP Design & Development Teams – Clock Macros/Register Files/Standard Cell/Benchmarking
• Managed teams to deliver IPs in the different technology nodes (28nm/20nm/16nm/14nm)
• Responsible for contractor management to ensure resourcing to achieve the deliveries as per the aggressive product schedules.
• Co-work with the US counterparts for ensuring quality and on time delivery.
• Worked along with the Chip Design and Cores (ARM A7/A53/A57) teams to provide optimal library usage guidelines for best PPA achievement analyzing critical paths and design requirements.

Jun 2008 – Mar 2013 · 4 yrs 9 mos · Bengaluru, Karnataka, India

• Standard Cell Library Benchmarking
• Analyzed 28nm TI Libraries by taking ARM Cores through complete synthesis and PNR flow to come up with new custom cells and tweaks in the libraries and flows to improve PPA.
• Intellectual Property (IP) Design
• Lead a team for the design/development of Efuse/ODP Controller and ODP cells (28nm/20nm)
• Developed parallel chain architecture for a faster autoload sequence for Bootup.
• Definition and Development of Slew Rate Compensated SMART (LVCMOS) IOs in 28nm technology node
• Worked closely with the OMAP IP and Architecture Team to come up with a slew rate compensated IO. The new IO architecture made use of PTV compensated Delay Line along with Process Compensated output driver to achieve a slew rate spread of 1.4X across PTV conditions which was around 5X in the previous technology node.
• Using a variable delay line, the IO can be configured for various slew rate specifications which helps the usage of the same IO for various board conditions, reducing development cycle time and resourcing.
• To achieve the above result single cycle lock DLL architecture was conceived which made use of dual counter approach to calibrate very low frequencies without any area penalty and still having a jitter resolution of one delay element. This eased the integration at OMAP level as using a high frequency clock and routing the same is a big overhead at SoC level in terms of area and power.
• Intellectual Property (IP) Design - DDR3 Architecture Definition and Development
• Worked with the SoC Architecture team to come up with a DDR3 PHY architecture. The new architecture closely interacted with the memory controller to implement the new features in DDR3 like the Write Leveling, Read Leveling and Increment Leveling.

Jul 2007 – May 2008 · 10 mos · Bengaluru, Karnataka, India

• Physical Design
• Responsible for the Floor Planning, Timing Closure and Physical Design Signoff Flow for multi power domain Blocks.

Jul 2001 – Jul 2007 · 6 yrs

• Physical Design
• Architected and developed a zero-touch IO(PAD) Ring Planning Flow for Wire Bond Designs resulting in 10X Cycle Time reduction
• Lead the activity of IO Ring Planning and Creation of various Wire Bond and Flip Chip ASIC Designs
• Intellectual Property (IP) Design and Development (DDR/QDR/RLDRAM)
• Physical Design Lead for development of the integrated DDR DDLL & IO Macro. The development of this macro is aimed at easing the Top-level integration of the DDR/DDLL Macros and to achieve better Area and Performance goals. This involved close interaction with Package/Signal Integrity/Flow Teams to enable a common macro for Wirebond and Flipchip designs. The PD involved full custom Power Mesh and maximize decap as well a full custom PNR Flow.
• Developed Memory Interfaces for DDR/DDR2/QDR/RLDRAM Standards.
• Design Standard Core Cell Libraries
• Developed a Theory Based on Logical Effort to generate a synthesizable library for desired cell architecture in any technology node based on an already existing library for architecture evaluation.
• Studied the effect of layout parasitic on the performance of cells and developed layout techniques to minimize the effects of parasitic and improve performance at cell level.
• Design of Retention Flops/ Integrated Clock Gating cell for leakage power reduction