Rajashekar Reddy Theegala

Software Engineer

Hyderabad, Telangana, India14 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expertise in multiple TSMC process nodes.
  • Proficient in physical design tools and methodologies.
  • Strong background in timing closure and place & route.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC physical design.

Contact

LinkedIn

Skills

Core Skills

Physical VerificationStaVery-large-scale Integration (vlsi)Timing ClosurePlace & Route

Other Skills

Design Rule Checking (DRC)VerilogVHDLFormal VerificationPerltclRedhawkMicrosoft ExcelASICGSMWireless

About

Worked on TSMC-7nm,16nm,28nm,40nm,150nm, INTL-10nm and GF-16nm. Macro count range from 12 to 857 Place and route using ICC2, FCCompiler, ICCompiler and Magma Timing signoff using Primetime Parasitic extraction using StarRC Physical verification (Calibre) Power Analysis (IR) using Redhawk EM using Redhawk

Experience

14 yrs 2 mos
Total Experience
2 yrs 10 mos
Average Tenure
4 yrs 7 mos
Current Experience

Amd

ASIC Physical Design Engineer

Oct 2021 – Present · 4 yrs 7 mos · Hyderabad, Telangana, India

Physical VerificationSTA

Intel corporation

ASIC Physical Design Engineer

Feb 2019 – Oct 2021 · 2 yrs 8 mos · Karnataka, India

  • Worked on 16nm lpddr and 7nm hierarchical block implimentation
Very-Large-Scale Integration (VLSI)

Mediatek

Senior Physical Design Engineer

Oct 2015 – Feb 2019 · 3 yrs 4 mos · Singapore

  • worked on TSMC-10nm,16nm,28nm and 40nm and worked on TSMC 40nm full chip Floorplan and timing
Timing ClosurePlace & Route

Intel corporation

Senior Physical Design Engineer

Mar 2015 – Sep 2015 · 6 mos · Penang, Malaysia

  • Worked on 14nm technology
Timing ClosurePlace & Route

Einfochips

Physical Design Engineer

Jan 2012 – Feb 2015 · 3 yrs 1 mo · Ahmedabad Area, India

  • Worked on TSMC-28nm, low power networking chip
Place & RouteVery-Large-Scale Integration (VLSI)

Education

srivekateswara eng college , suryapet

Engineer's Degree — Economics

Jan 2006 – Jan 2010

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