Saral Aggarwal

Software Engineer

San Jose, California, United States10 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Digital Circuit Design and Embedded Systems.
Hands-on experience with RTL design and formal verification.
Proven track record in SOC design engineering.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in digital circuit design and verification.

Contact

Skills

Core Skills

Digital Circuit DesignEmbedded SystemsFormal Verification

Other Skills

C++CMatlabMicrosoft ExcelMicrosoft OfficeProgrammingResearchMicrocontrollersMicrosoft WordPCB DesignEagle PCBJavaCadence VirtuosoCadence EncounterNC-Verilog

Experience

10 yrs 7 mos

Total Experience

3 yrs 6 mos

Average Tenure

4 yrs 8 mos

Current Experience

Amd

2 roles

Senior Staff Design Engineer

Promoted

Jul 2024 – Dec 2024 · 5 mos · Santa Clara, California, United States

Staff Design Engineer

Sep 2021 – Present · 4 yrs 8 mos · Santa Clara, California, United States

C++CMatlabMicrosoft ExcelMicrosoft OfficeProgramming+20

Qualcomm

3 roles

Senior Design Engineer

Promoted

Sep 2019 – Sep 2021 · 2 yrs

Low Power Design And Verification Engineer

Feb 2017 – Sep 2019 · 2 yrs 7 mos

Digital Design Intern

May 2016 – Sep 2016 · 4 mos · San Jose, California

Working with Server SOC front end design engineering team
Run the implementation flows like PLDRC (Spyglass- Pre Layout Design Rule Check) and CDC (0-in CDC Clock Domain Crossing) on full server SOC chip
Gained hands on experience with RTL based design using Verilog and formal verification using System Verilog Assertions
Designing the tool flow for formal based verification and equivalence checking in Jasper