Rajul Jain — Software Engineer

Contributing to the verification of diverse functionalities in CPU subsystem. Core contributions include running regression and debugging of critical flows such as Boot Memory redundancy Debug Scandump Clock & Reset Other major responsibilities include Formal verification where I learnt about formal property verification for small finite state machines by writing multiple simple assertions/ properties along with appropriate covers and assumes. Key concepts cover convergence, complexity, debugging failing assertions, understanding counter examples. Previously I have worked on GPU sub-system verification. There I used to run and analyze regression along with debugging, analysing function coverage & code coverage, writing Systemverilog assertions, checkers, addition of bus functional model, writing tests to cover different scenarios in SystemVerilog and OVM. I am a proactive and curious professional, eager to work on cutting edge technologies with greatest minds while focusing on continuous growth. Over time, I have acquired three important skills - 1. Collaborations & team work 2. Adaptability 3. Effective and concise communication

Stackforce AI infers this person is a VLSI verification engineer with expertise in functional and formal verification methodologies.

Location: Sabalgarh, Madhya Pradesh, India

Experience: 8 yrs 10 mos