Ashwin K N

Software Engineer

Bengaluru, Karnataka, India8 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in PPA and test chip activities.
Experience with RTL2GDSII CPU core designs.
Strong collaboration skills across teams.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in ASIC and VLSI.

Contact

Skills

Core Skills

Physical DesignStatic Timing AnalysisAsic

Other Skills

eda toolVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)CMicrosoft OfficeUnixVerilogPerlReal-Time Operating Systems (RTOS)VHDLC (Programming Language)Thin FilmsIC compiler 2Design CompilerTcl-Tk

About

Physical design engineer with PPA expertise, test-chips and cross team collaboration experience in RTL2GDSII CPU core designs. Bachelor's degree in electronics and communication from R V College of Engineering, Bangalore.

Experience

8 yrs 7 mos

Total Experience

2 yrs 10 mos

Average Tenure

3 yrs 11 mos

Current Experience

Google

Physical Design Engineer

Jun 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India

Static Timing AnalysisPhysical Designeda toolVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)C+17

Intel corporation

ASIC Physical Design Engineer

Nov 2018 – Jun 2022 · 3 yrs 7 mos · Bengaluru, Karnataka, India

PPA and test chip activities. RISC V( Horse creek) and ARM CPU cores block implementation. Horse creek SoC being Sifive's first RISC V P550 core with Intel's leadership IPs DDR5 and PCIe.

PPAtest chip activitiesRISC VARM CPU cores block implementationDDR5PCIe+2