Vinay Padade

Software Engineer

Bengaluru, Karnataka, India4 yrs experience

Key Highlights

  • Expert in Static Timing Analysis and Logic Synthesis.
  • Proficient in Physical Design and Floorplanning.
  • Strong background in ASIC and SoC design.
Stackforce AI infers this person is a Semiconductor Design Engineer specializing in ASIC and SoC development.

Contact

Skills

Core Skills

Physical DesignFloorplanningLogic SynthesisStatic Timing Analysis

Other Skills

CLPFusion CompilerGenusSystem on a Chip (SoC)LECDigital DesignsCMOSOptimizationApplication-Specific Integrated Circuits (ASIC)PnRVerilogCTSICC2

Experience

4 yrs
Total Experience
2 yrs 11 mos
Average Tenure
1 yr 1 mo
Current Experience

Confidential

Senior Design Engineer

Apr 2025Present · 1 yr 1 mo · Greater Bengaluru Area · On-site

CLPFloorplanningPhysical Design

Mediatek

Synthesis and STA Engineer

Apr 2022Mar 2025 · 2 yrs 11 mos · Greater Bengaluru Area

Logic SynthesisStatic Timing Analysis

Education

University of Mumbai

Bachelor's degree — Electronics Engineering

Stackforce found 100+ more professionals with Physical Design & Floorplanning

Explore similar profiles based on matching skills and experience