Aug 2015 – Jan 2016 · 5 mos · Santa Clara, CA

May 2001 – Mar 2015 · 13 yrs 10 mos · Sunnyvale and Hyderabad India

•  Built a team (management and engineering) in India to develop complex SOC’s. Grew the team to 300+ engineers in 5 years. Started with a few functions initially and eventually developed all chip design skills in the design center – Architecture, Technology, Methodology, RTL design and integration, Design Verification, Performance validation and tuning, Synthesis and Physical Design, DFT, Emulation, post-silicon debug and Program management.
•  Built a global team of 100+ engineers in multiple sites – Sunnyvale, Austin, Boston, Bangalore. Team was responsible for developing derivative products, and optimizing products for performance, power, yield and cost.
•  Led the development of the first native dual-core x86 microprocessor code-named JackHammer (Opteron) – the most successful server product for AMD. Responsible for defining, developing and validating the dual-core implementation methodology.
•  Project leader for the first x86 APU SOC (Brazos) – a very successful mobile PC product for AMD. Responsible for all functions of SOC design – project scoping and planning, architecture and definition, RTL development and integration, verification and emulation, DFT, design methodology, physical design, chip bringup/validation and productization collaboration/support.
•  Project leader for the first Southbridge integrated x86 APU SOC – taking it from design to production in less than 2 years. The product had several power optimization features which enabled 50% more battery life than its predecessors.

Jan 1997 – Jan 2001 · 4 yrs · Campbell, CA

•  Led a team of 30+ logic/circuit designers and 20+ layout contractors to design SPARC compatible 1 GHz microprocessors in 0.18u process with 6 Metal layers. Responsible for the logic/circuit design and layout of all the non-memory full-custom modules in the microprocessor - Floating Point unit, Fixed Point Unit, Load-Store Unit, Instruction Fill Unit, and Fixed and Float Register files. Responsible for project planning and management.
•  Defined the FPU and Graphics Unit microarchitecture and worked with the performance group to evaluate and tune performance. Responsible for the RTL design and verification of the Floating Point Unit.
•  Interfaced with the circuit and layout teams on design methodology and strategy. Established guidelines for the layout of datapath and full-custom blocks. Interfaced with the foundry for technology rule decks tuning.

Jan 1992 – Jan 1996 · 4 yrs · Dallas, TX

•  Unit lead on the Integer execution unit and Address Calculation Unit of 400 MHz M3 microprocessor. Responsible for RTL coding, unit level functional verification, and circuit design of these units.
•  Floating Point Unit leader responsible for the FPU and its interface to the core, cache, and the bus controller of the 150 MHz GX microprocessor. Responsible for the logic design, circuit design, floorplan, and timing analysis. Did the full chip timing analysis (setup and hold) using pearl.
•  Floating Point Unit leader for the 50 MHz M7 microprocessor. Responsible for the microcode of complex instructions, RTL coding of the FPU, logic design, and circuit design. Worked on porting the design to IKOS hardware accelerator for gate level simulation of the design.

Jan 1988 – Jan 1992 · 4 yrs · Austin, TX

•  Principal engineer responsible for all phases of the Multiplier (Interger and Floating Point) Unit of 50 MHz 88110 microprocessor.
•  Defined the microarchitecture and performed feasibility analysis.
•  Wrote RTL code in M language and did functional verification using Lsim.
•  Did the logic and circuit design of the 3-cycle super-pipelined extended precision (80-bits) multiplier fully compliant with IEEE-754.
•  Did the floorplan and layout of core cells like the CSA. Wrote layout generators for integrating the multiplier datapath.