Anurag Sharma — Director of Engineering

Seasoned professional in SoC / SubSystem / IP Verification activities based on verification methodologies like UVM / TLM. Functional Verification using HIGH-Level languages, Gate-level simulation, Low-Power Verification and SoC Verification. Formal Property Verification for CPU Blocks using JG by Cadence & vcf by Synopsys. Specialities: Verilog, System Verilog, C/Cpp , SVA, Python, Perl, TCL Methodologies Knowledge - TLM, UVM Protocols - MMC/eMMC/SD/SDIO Cards, SPI Controller, STBUS, AXI Bus, AHB Bus, APB Bus, Flash Memory Controllers. CORE Knowledge - IP Functional Verification strategies, Digital Design, Memory Controllers, CPU Functionality, Caches and Coherency, SoC global Clock and RESET controllers, PMU

Stackforce AI infers this person is a semiconductor verification expert with a focus on SoC and IP development.

Location: Bengaluru, Karnataka, India

Experience: 15 yrs 3 mos