Mar 2022 – Oct 2023 · 1 yr 7 mos

• 1. Contributed to the refinement of Advanced IR signoff methodologies including ROM, IR-ECO, and SigmaDVD, actively participating in customer evaluations and engagements for these enhanced workflows.
• 2. Pioneered the creation of automated flows aimed at generating V2V correlation reports and conducting comprehensive analyses of runtime data (Deep Dive) to improve tool performance.

Jul 2020 – Mar 2022 · 1 yr 8 mos

• 1. As a Product Specialist for Ansys' flagship product RedHawk-SC, a best-in-class sign-off and EMIR analysis tool, I worked on EMIR simulation flows such as Dynamic and Static IR, EM, 3DIC, CPM, etc.
• 2. Additionally, I assisted some of the top SOC manufacturers in the world with setting up traditional chip sign-off processes, such as vector-based and vector-less static and transient EMIR analysis, in collaboration with their CAD teams.
• 3. I also gained experience in working with sophisticated flows like Ramp-Up, 3DIC, and Thermal analysis, which are becoming more crucial as newer tech nodes come up.

Jun 2019 – Jul 2019 · 1 mo · Delhi

• Interned at the VLSI Laboratory at Delhi Technological University under the guidance of college professor Dr. Rajeshwari Pandey.
• During the internship first proposed the design of Analog Current Distribution Transconductance Amplifier using 90nm technology node. Using modified high swing cascode current mirror in the CTDA, improved the the linear range of operation and lowered the input impedance. Implemented the validated the proposed design using OrCAD PSpice Tool.
• Also Designed the Layout of CDTA block using Cadence Virtuoso and achieved 99.6% accuracy between the layout and the schematic.