Mar 2010 – Oct 2011 · 1 yr 7 mos · Bengaluru, Karnataka, India

• Mentoring Interns
• Mentored an Intern to come up to speed in System Verilog and implement Functional Coverage
• 100G MAC Verif
• Lead the verification effort
• Test plan
• Schedule
• VMM based env/test cases/Scorebard etc
• Test chip Full chip verification (10m/100m/1G/10G/40G)
• Lead the verification effort
• Test plan
• Schedule
• VMM based env/test cases/Scorebard etc
• Subsystem level verification
• Created a very flexible env which helps to change the DUT/project config and get up the verif env very very fast for any Config
• Customer presentations for verification like test plan
• Lead Engineer
• Test plan
• Schedule
• VMM based env/test cases
• Random tests

Jul 2006 – Mar 2010 · 3 yrs 8 mos

• Silicon proven Strong Modelling/Verification/Test Plan/Test case/Module lead skills
• Involved in Verification of multimillion gate ASICs/IP of complex networking chips.
• Owned/Built SystemC reference models design from scratch for a Major Block
• Owned/Built verification envs in SystemVerilog from scratch.
• Owned LEC flow setup for diff stages backend stages from scratch for multiple silicon proven chips
• Involved in Performance verification of Silicon Proven MACSec IP
• Involved in Full chip GLS/Verplex/ECOs/Reference Model/Verification of a silicon proven FC chip

Mar 2002 – Jul 2006 · 4 yrs 4 mos

• Silicon Proven FV/Emulation/GLS/Validation skills
• 2+ years of extensive experience in setting up Emulation setup with palladuim with RTL/netlist flow.
• Was responsible for setting up an emulation setup for an Ethernet switch with netlist/RTL flows. Instrumental in packing 2 huge design in a emulator, improving productivity by 2x.
• Won 2 SRAs, 1 for PCI validation and 1 for emulation
• Was responsible for verification for Qos/PCI interface of a Ethernet chip.
• Also responsible for board bringup of a ethernet chip. Won DRA for a very speedby bringup of the chip. Provided enough support to fibbing team for a timing correction in XAUI interface.
• Was responsible for GLS of 3 GMCH chips. (1 SRA for this activity)
• Was fully responsible for power validation in GLS of a graphic partition.
• Was responsible in setting up a GLS flow for a memory controller interface.
• Was fully responsible for the FV/ECO flow setup for a stepping of a GMCH chipset in india.
• Was responsible for training people the FV setup flow for GMCH chipsets.

Nov 1999 – Mar 2002 · 2 yrs 4 mos

• Worked on 2 projects
• First project included board schematics development, board debug, FPGA design, testbench development in VHDL and verification. Also included was FPGA backend tools. FPGA was designed to augment an existing conextant ATM chip.
• Second project was intended to work as a graphic processor. Designed an FPGA interface to work with a PCI-X core. Also was responsible for setting the verification flow in VHDL.