Tapas Ray

DevOps Engineer

Bengaluru, Karnataka, India28 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led verification of Serdes PHY and PCS IPs.
Designed a 50G QoS FPGA for WiFi applications.
Managed teams delivering complex semiconductor projects.

Stackforce AI infers this person is a Semiconductor and Networking expert with extensive FPGA and ASIC design experience.

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Skills

Core Skills

AsicFpgaDesignRouting

Other Skills

VerificationTeam ManagementSerdes IPQuality of ServiceBaseband DesignCMTSEmbedded SystemsLinuxPerlDebuggingEthernetUnixSystem ArchitectureLTEAlgorithms

About

Deep technical expertise in ASIC/FPGA verification, proven leadership skills with building teams from scratch, multi site collaboration and project execution, and delivering on time with high quality. Managed the worldwide verification of entire line of Serdes PHY (32G, 56G and112G) and PCS (PCIe, USB and SATA) in Rambus. Taped out 10+ Serdes IP's in 7nm-28nm in last 5 years. Extensive experience in designing with FPGA's for IP Networking applications for two successful startups. Focus on customer satisfaction through interactions for pre-sale, verification execution and customer support.

Experience

28 yrs 7 mos

Total Experience

4 yrs

Average Tenure

5 yrs 3 mos

Current Experience

Intel corporation

Verification Manager

Mar 2021 – Present · 5 yrs 2 mos · Bengaluru, Karnataka, India

Rambus

Verification Manager

Jul 2015 – Dec 2020 · 5 yrs 5 mos · Bangalore

Managing a team of over 30 engineers with complete ownership and responsibility of worldwide Serdes IP verification
Delivered over 25 IP's in last 5 years.
Taped-out 5 Test Chips with PHY's in 32G and 112G rates
Led the development of Generic PHY and Unified PCIe VIP

ASICFPGAVerificationTeam ManagementSerdes IP

Benu networks

Senior Manager

Mar 2011 – Jul 2015 · 4 yrs 4 mos · Greater Boston Area/Bangalore

Designed a 50G Hierarchical Quality of Service FPGA with 375K Queues and 512K rate limiters supporting WRR, DWRR and RR scheduling for the WiFi Access Gateway.
Led a team of 8 engineers to architect, design and verify the design.
Designed the Packet Buffering, Queue/Buffer Descriptor Engine, Free Buffer Pool Manager, Statistics Engine modules

FPGAQuality of ServiceDesignVerification

Cisco systems india

Manager, Hardware Engineering

Aug 2008 – Jul 2010 · 1 yr 11 mos · Bengaluru Area, India

Led a team of 4 engineers to build a baseband FPGA for Cisco's WiMax base station.

FPGABaseband DesignTeam ManagementDesign

Motorola

Principal Engineer

Jan 2000 – Jul 2008 · 8 yrs 6 mos · Greater Boston Area

Developed the Fast Path Engine (FPE) for BSR64K, an enterprise class, chassis based CMTS/Edge Router, for River Delta Networks and later acquired by Motorola. Implemented and verified the following features in the FPGA:
IPv4/IPv6 IP Destination Address and MPLS Label look up, MPLS Label Pop-Swap-Push.
IP Encapsulation and De-encapsulation, Ingress and Egress Access List and Policy Based Routing.
Interfaces to external devices like LPM, CAM and QDR-II SRAMs.

FPGACMTSRouting