konark patel — Software Engineer

As a verification engineer I am having a understanding and experience of, ☛ RTL Verification ☛ IP level verification using SV and UVM. ☛ Test bench development, test case coding and execution from scratch ☛ Regression debugs, Coverage analysis ☛ Protocol knowledge Ethernet,OTN etc. ☛ Validation test creation using Python Good understanding of ASIC flow, FPGA flow, ☛ Knowledge of System verilog and verilog. ☛ Knowledge of System UVM. ☛ Knowledge of OTN Network. ☛ Ability to work in group and problem solving skills. ☛ Prolific at Communication ☛ good knowledge digital design. TECHNICAL SKILLS : ☛ Hardware Description Language(HDL): Verilog, Syatem verilog ☛ Programming Languages: C ☛ Scripting Languages: Python ☛ Worked on Semi-custom design Tools: Cadence NCVerilog, Cadence RTL Compiler, Encounter RTL to GDSII, Xilinx ISE, ModelSim ☛ Full Custom design Tools: Virtuoso ADE/Layout XL ☛ Computing Platforms: Windows, Unix(Working knowledge), gvim editor, Microsoft Office

Stackforce AI infers this person is a Verification Engineer specializing in ASIC and FPGA design within the Semiconductor industry.

Location: Ahmedabad, Gujarat, India

Experience: 10 yrs 8 mos