Ankita Saha — Software Engineer

Enthusiastic about Frontend RTL Design Verification using Perl and SystemVerilog. Passionate about Design verification methodologies. Interests & Experience - ☛ Master's Thesis work on coverage analysis (functional coverage, code coverage) using IMC ☛ Currently working on verification of interconnect protocols and Register bus. ☛ Efficient with scripting languages such as Perl, System Verilog and TCL(Coverage flow automation). ☛ Worked on developing checkers from scratch and writing Assertions. ☛ Familiar with Verification debugging tools such as Verdi, Sim Vision, coverage tool IMC ☛ Actively involved in test plan development for IP verification. ☛ Experienced in directed testing by performing careful analysis of corner ccases.As well as random test scenarios generation as per protocol, by scripting. ☛ Worked on ASIC projects in the pre silicon design verification team. Technical skills: ☛ Hardware Description Language : Verilog, SystemVerilog for Design Verification, SystemVerilog Assertions (SVA). ☛ Protocols - Worked on AMBA AXI & ACE protocols. ☛ Scripting Languages : Perl, Tcl, C++ ☛ Revision Control : git ☛ Tools : Synopsys Verdi, Cadence Sim Vision for debugging. Cadence Xcelium and Synopsys VCS for compilation. Coverage tool Cadence IMC.

Stackforce AI infers this person is a Design Verification Engineer with expertise in VLSI and hardware verification.

Location: Bengaluru, Karnataka, India

Experience: 5 yrs 10 mos