Jun 2022 – Sep 2025 · 3 yrs 3 mos · Bengaluru

• On‑Die EMIR Signoff Lead – Google Pixel CPUs
• Led end‑to‑end Power Integrity (PI) and Electromigration (EM) signoff for high‑performance blocks and the flat CPU in Google’s latest Pixel processors.
• Drove EMIR closure on advanced 2nm and 3nm technologies with TSMC and Samsung, balancing aggressive performance, power, and reliability targets.
• Used Ansys RedHawk‑SC for full‑chip Static/Dynamic IR drop and Signal EM analysis on critical CPU blocks.
• Owned Power Delivery Network (PDN) signoff, collaborating closely with design, physical implementation, STA, and package teams to ensure convergence.
• Performed RDL/Bump planning and package‑aware simulations to guarantee robust, system‑level power delivery.
• Enabled IR‑aware timing and Vmin analysis flows to validate silicon performance and reliability margins.
• Developed and deployed a Power Number–based methodology to guide efficient Power EM optimization and design trade‑offs.On‑Die EMIR Signoff Lead – Google Pixel CPUs

Dec 2019 – Jun 2022 · 2 yrs 6 mos

• Power Integrity / IR Drop / EM Signoff – Mobile CPU (Snapdragon Processors)
• Led Power Integrity, IR Drop, and Electromigration (EM) signoff for high‑performance mobile CPU blocks and flat CPUs in flagship Snapdragon SoCs.
• Used Ansys RedHawk‑SC to perform comprehensive EMIR analysis, ensuring robust power delivery and reliability across advanced nodes.
• Executed PDN (Power Distribution Network) signoff on 4nm, 5nm, and 7nm TSMC and Samsung technologies, addressing deep sub‑micron design and reliability challenges.
• Managed multiple PDN signoff projects end‑to‑end, coordinating with PD, STA, Power, and Package teams to achieve on‑time closure.
• Drove RDL (Redistribution Layer) and bump planning to optimize package‑level and system‑level power delivery for mobile CPUs.
• Performed package‑aware simulations to identify and mitigate system‑level PI risks early in the design flow.
• Enabled IR‑aware timing and Vmin analysis, securing functional stability and performance margins under realistic power variation conditions.Power / IR Drop / EM Signoff – Mobile CPU (Snapdragon Processors)

Mar 2017 – Dec 2019 · 2 yrs 9 mos

• Power, IR Drop and EM Signoff of Mobile CPUs, using Ansys Redhawk
• Technology used: 10 nm, 5 nm finFET (Samsung Foundry) & 7nm finFET (TSMC Foundry)

Jun 2015 – Feb 2017 · 1 yr 8 mos

• Power, IR Drop and EM analysis of Mobile CPUs, using Ansys Redhawk
• Technology used: 28/14/11 nm finfet Technology on Samsung / TSMC Foundry
• About Project work-
• Worked on latest Snapdragon Processor CPU blocks and flat CPU for IR drop /EM Signoff
• Floor plan exit, PRO exit PDN reviews for sanity checks and other power grid related issues
• Static / Dynamic IR Drop and Signal EM simulations for CPU blocks & full flat CPU
• Identified Regions of violation and suggested remedies to design Power grid efficiently and prepare cells, Macro placement / Hook up strategies
• IR simulations for deciding the area and count of switches needed in design
• RDL/Bumps planning over CPU, and then running pre-simulations using Redhawk GPS

Jan 2014 – Dec 2014 · 11 mos · Greater Noida

• Project topic: IR Drop/ EM analysis of Digital IP’s and AMS IP’s using Ansys RedHawk
• Technology: 28 nm FDSOI Technology on STMicroelectronics Foundry
• About Project work -
• To develop understanding & flow setup within team
• Worked on Digital and AMS IP’s for IR drop /EM Analysis
• Identified potential locations and Regions of violation to design Power grid and use of Decoupling capacitor in an efficient way
• Generated CMM views to be included in RedHawk for electrical and physical characterization of Analog IP’s
• Generation of CPM for delivering to customer for package level simulations

Jan 2013 – Dec 2013 · 11 mos · BITS Pilani

• Responsibility: To take Tutorials and Labs
• Digital Design, solving problems from logic gates, combinational, sequential, state Diagrams and State machines both theoretically and then implementation on Bread Boards
• Simulating Digital problems on Modelsim and Xilinx using Verilog Language, for Verification and synthesis
• Microprocessor, Understanding of Instruction set and Assembly language Programming of x86 Intel Processor Family
• Simulating Assembly Language programs on MASM, a simulator