Rajasekar Raman

Software Engineer

Bengaluru, Karnataka, India15 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in power and signal integrity sign-off.
Proven track record in mitigating IR drop risks.
Strong collaborative approach ensuring project success.

Stackforce AI infers this person is a specialist in Electrical Engineering with a focus on Power Integrity and Signal Integrity.

Contact

Skills

Core Skills

Power DeliveryElectrostatic Discharge (esd)On Die + Pkg OptimizationPdnCodesign PackageRedhawk

Other Skills

OndieStatic IR AnalysisDynamic IR AnalysisPower Grid Design optimisationFmax prediction based IR and STA integrationBest IR annotated Vmin strategyPCB and package carry on optimisation strategy for on-die IR drop simulationIR sign off Methodology refinement for better PPAElectromigrationVminFmaxIP Integration Sign OffSilicon Vmin Root Cause AnalysisApplication-Specific Integrated Circuits (ASIC)Debugging

About

At Qualcomm, my focus has been on advancing the field of power and signal integrity sign-off, with a particular emphasis on mitigating early-stage IR drop risks and designing robust power grid structures. The team's efforts in power and ground bump location estimation have been pivotal in enhancing system reliability. Leveraging expertise in Electromigration and Redhawk, we have successfully executed complex block projects with quality, on time. Our collaborative approach has enabled us to consistently deliver quality outcomes, ensuring successful project execution and contributing to Qualcomm's reputation for excellence in electrical engineering.

Experience

15 yrs 9 mos

Total Experience

3 yrs 11 mos

Average Tenure

8 yrs 10 mos

Current Experience

Qualcomm

3 roles

Senior Staff Engineer

Promoted

Dec 2022 – Present · 3 yrs 5 mos

Electrostatic Discharge (ESD)Power Delivery

Staff Engineer

Jan 2020 – Dec 2022 · 2 yrs 11 mos

Electrostatic Discharge (ESD)On Die + PKG optimization

Sr.Engineer Lead

Jul 2017 – Jan 2020 · 2 yrs 6 mos

PDNCodesign PackageOndie

Mediatek

Senior Physical Design Engineer

May 2014 – Jul 2017 · 3 yrs 2 mos · Singapore

Power Switch Estimation and Grid Selection based Performance and Power Hungry of Blocks
Analyse the health of PDN such as Grid check, Static, Dynamic (Vless and VCD), In-Rush Simulation.
Overall SoC Power Noise Reliability Sign-Off

PDNCodesign PackageOndie

Apache design solutions (subsidary of ansys)

Application Engineer

Oct 2012 – May 2014 · 1 yr 7 mos · Bangalore

Pre and post sale support for apache products such as RedHawk & Totem
Product Validation and Benchmarking

PDNCodesign PackageOndieRedhawk

Wipro limited

Physical Design Engineer

Aug 2010 – Oct 2012 · 2 yrs 2 mos · Bengaluru, Karnataka, India

Physical design using Synopsys and Magma EDA tool respectively.
Various Physical Design and Development based on
Basic CMOS Gate Layout Design using Cadence Virtuoso.
Physical Design Flow using Magma & Synopsys EDA tool.
Layout verification using Calibre, Hercules
Floor Planning, Placement ,Clock Tree Synthesis, Routing and Sign off checks
Layout Verification Project which consist of Design Rule Checks (DRC), Antenna Violations, Layout Versus Schematic (LVS), Density cleaning