Peeyush Bhardwaj — Software Engineer

• With over 3 years of experience in design verification throughout the chip development process, I have developed extensive knowledge in protocols and logic design, specializing in design verification. • Worked in IP verification and RAL verification. • Experience in verifying IP functionality through the development of test cases, functional coverage analysis, debugging and the application of UVM for ensuring design correctness. • Hands-on experience with Synopsys VCS, Verdi, Questasim, Quartus prime, Xilinx ISE EDA tools. •3 years of experience in IP level verification •Designed UVM testbenches for Peripheral IPs like Pulse width Modulation (PWM), APxGPT, Keypad, Infrared Receiver etc. •Developed test cases and implemented Assertion-Based Verification methodologies to verify functional correctness, performance and compliance with specifications. •Executed simulation tests, debugged failures, and tracked issues using bug tracking tools. •Designed and executed test cases to achieve high functional coverage and identify corner-case scenarios, reducing design risks. •Collaborated closely with design and architecture teams to resolve the root cause of RTL design issues and optimize performance. •Implemented RAL-based verification environments to enable comprehensive verification of register interfaces and functionality. •Good experience with the EDA tools like Synopsys VCS, Verdi, Mentor Graphics Questa sim, Quartus prime, Xilinx ISE. •Hand’s on experience on constraint driven verification •Hands on experience on dynamic CDC & formal wdr verification Behavioural Skills :- •Focused •Consistent •Punctual •Leadership & Team work •Communication skills •Good listener

Stackforce AI infers this person is a Design Verification Engineer specializing in VLSI and ASIC industries.

Location: Bengaluru, Karnataka, India

Experience: 3 yrs 2 mos