Naveen D S — CEO
• Experienced in SOC/IP level verification. • Block level Verification based on System Verilog UVM Environment • Developed test bench environment for Block level Verification Using Existing UVC’s. • Understand OOPs Concepts (System Verilog), Verification plan, Debugging • Good understanding of UVM hierarchy, and its environment. • Knowledge of AMBA AXI, AHB, APB protocols • Worked on formal equivalence checking of RTL vs Post Routed Netlist and RTL vs Pre-Routed Netlist using formality tool • Debugging failures •Debug, report, and work closely with design engineers. Develop SystemVerilog/UVM testbenches at Top/Sub-system/Block-levels •Extending existing verification environments to improve the quality of testing •Involved in writing and modifying tcl scripts
Stackforce AI infers this person is a VLSI verification engineer with expertise in SOC and IP verification.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 3 mos
Skills
- Universal Verification Methodology (uvm)
- Ip Verification
- System Verilog
- System On A Chip (soc)
Career Highlights
- Expert in SOC/IP level verification.
- Proficient in System Verilog and UVM environments.
- Strong background in debugging and verification planning.
Work Experience
Eximietas Design
Technical Lead (2 mos)
Module leader (1 yr 6 mos)
Intel Corporation
Contigent worker (10 mos)
Etched
IP Verification Engineer (10 mos)
Qualcomm
Contingent worker (5 mos)
Meta
Contingent worker (9 mos)
Capgemini Engineering
Lead Software Engineer (1 yr 10 mos)
AMD
Contingent worker (5 mos)
L&T Technology Services Limited
Verification Engineer (5 yrs 1 mo)
Esencia Technologies Inc.
Intern (6 mos)
Dell
sr executive (1 yr 2 mos)
Education
Master of Technology - MTech at Iit jammu
Bachelor of Engineering (BE) at The oxford college of engineering
High School/Secondary Certificate Programs at sree vidyanikethan international school
