Divya R — Software Engineer

Proficient with Functional Verification using Verilog and System Verilog which involves features extraction and verification plan development, Testbench bring-up, implementation of Checker, Test cases development with random stimulus generation, Functional Coverage and Code Coverage Implementation of RTL in Verilog and Testbench environment in System Verilog Good Knowledge in Verilog HDL, Self-checking Testbench and Testbench in System Verilog Writing test cases, develop System Verilog Testbench components and good problem solving and debugging skills Good understanding of the ASIC Verification Flow and Testbench architecture Created functional tests and worked on Code and Functional Coverage closure Have undergone extensive training in System Verilog and UVM methodology Knowledge of assertion and coverage driven verification with Constrained Random Testing (CRT).

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and RTL design.

Location: Bengaluru, Karnataka, India

Experience: 10 yrs 4 mos