Khalid Qureshi

Director of Engineering

Hyderabad, Telangana, India25 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in hardware IP development and verification.
  • Proven leadership in managing silicon design teams.
  • Strong background in SoC integration and verification.
Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in hardware design and verification.

Contact

LinkedIn

Skills

Core Skills

Verification

Other Skills

Hardware securityCoordinationSystem level verificationASICSoCSystemVerilogFunctional VerificationVLSI

About

Semiconductor Industry : Experienced in hardware IP development, design & Verification. Experienced in SoC integration and verification. Experienced in dealing with SOC platforms with multiple processors and memory subsystem. Specialties: RTL verification and design. Testbench architecture and environment development.

Experience

25 yrs 1 mo
Total Experience
4 yrs 2 mos
Average Tenure
4 yrs 3 mos
Current Experience

Amd

Sr Manager Silicon Design Engineering

Feb 2022 – Present · 4 yrs 3 mos · Hyderabad, India

Xilinx

5 roles

Sr Design Engineering Manager

Jul 2021 – Feb 2022 · 7 mos

Design Engineering Manager

Jul 2015 – Jun 2021 · 5 yrs 11 mos

Design Engineering Section Manager

Promoted

Aug 2013 – Jun 2015 · 1 yr 10 mos

Sr Design Engineer-2

Oct 2010 – Aug 2013 · 2 yrs 10 mos

  • Hardware security exposure during Boot ROM verification.
  • Coordination with software/emulation teams.
  • Mentoring jr. team members.
  • Responsible for multiple blocks and System level verification.
  • Working on Coresignt Components, Cortex A9 based system, PL330 DMAC, GateLevel Simulation etc

Sr Design Engineer 1

Nov 2009 – Sep 2010 · 10 mos

Sasken

Lead Engineer

Aug 2004 – Dec 2009 · 5 yrs 4 mos

  • Joined Sasken as Sr. Design Engineer, Current designation is Lead design engineer.

Hcl technologies

Sr. Member Technical Staff

Mar 2004 – Aug 2004 · 5 mos

Cg coreel

Application Engineer DFT

Sep 2003 – Mar 2004 · 6 mos

  • Supported Motorol for mentor DFT tools.

Wipro technologies

Design Engineer

Jan 2001 – Sep 2003 · 2 yrs 8 mos

  • This was my first exposure into the area of VLSI design. Wher I had worked on AMBA AHB primecells (Soft IPs).

Instrumentation limited, government of india enterprise

Contract Engineer

Apr 1999 – Jun 2000 · 1 yr 2 mos · Kota, Rajasthan, India

Education

CDAC - ACTS, Hyderabad

PG Diploma — VLSI Design

Jan 2000 – Jan 2000

University Engineering College, Kota

Bachelor of Engineering - BE

Jul 1994 – Sep 1998

Engineering college KOTA

Electronics and comminication

Jan 1995 – Jan 1998

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