Shivakumar Agumbe Nagaraj

Software Engineer

Bengaluru, Karnataka, India14 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 13 years of ASIC Verification experience.
Expert in SystemVerilog and UVM methodologies.
Proven track record in complex SoC verification projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in ASIC and SoC verification.

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Skills

Core Skills

SystemverilogUvmVmm

Other Skills

VerilogFunctional VerificationASICSoCInterlakenVCSPerlSemiconductorsGigabit EthernetDebuggingVLSIRTL verificationVerdiBlock Level VerificationSimulations

About

• 13+ years of industry experience in ASIC Verification. • Proficient in SystemVerilog, Verilog. • Experience in both IP/block level verification and System level verification (SOC). • Verification Methodologies: UVM, VMM. • Experience in feature extraction, writing test plan, building verification environment, writing functional tests, coverage plan, functional coverage and code coverage closure. • Have worked in UPF low power verification and Gate level simulations. • Familiar Protocols: SPI, UFS, D-PHY, C-PHY, Interlaken, AMBA AHB.

Experience

14 yrs 8 mos

Total Experience

2 yrs 11 mos

Average Tenure

5 yrs 3 mos

Current Experience

Qualcomm

Staff Engineer

Feb 2021 – Present · 5 yrs 3 mos · Bengaluru, Karnataka, India

SystemVerilogVerilogUVMFunctional VerificationASICSoC

Marvell semiconductor (acquired aquantia in sep 2019)

Senior Engineer

May 2017 – Feb 2021 · 3 yrs 9 mos · Bengaluru, Karnataka

Broadcom limited

Senior Design Verification Engineer

Nov 2014 – May 2017 · 2 yrs 6 mos · Bengaluru Area, India

Sicon design technologies pvt. ltd.

ASIC Verification Engineer

Aug 2012 – Oct 2014 · 2 yrs 2 mos · Bangalore

1: Verification of HST-Rx block.
Client : Broadcom Limited
Language : SystemVerilog
Methodology : UVM
Role in project :
· Created test plan for LBIST , PRBS and coded the test cases.
· Contributed in creation of test plan of Interlaken PCS tests.
· Coded all the Interlaken/ILA PCS tests.
· Debugged PCS, LBIST and PRBS tests.
2: Verification of Interlaken Controller
Client : AppliedMicro
Language : SystemVerilog
Methodology : UVM
Description : Interlaken is a high-speed channelized chip-to-chip interface. It is optimized for high-bandwidth and reliable packet transfers. It has a simple control word structure to delineate packets, supports multiple channels, backpressure capability, and data-integrity protection to boost the performance of communications equipment.
Role in project :
· Contributed in creation of test plan for Interlaken controller.
· Understood the third party VIP.
· Created functional tests to verify controller.
· Worked on functional coverage closure at FIP level.
· Creating and verifying use cases with different packet profiles and flow control scenarios at top level.
3: Verification of TX Interface and Scheduler
Client : AppliedMicro
Language : SystemVerilog
Methodology : UVM
Role in project :
· Created test plan for TX Interface
· Built UVM environment around TX Interface and verified the same
· Verified scheduler for fair share in bandwidth
· Created functional tests and worked on coverage closure.
4: Verification of RX Interface
Client : AppliedMicro
Language : SystemVerilog
Methodology : UVM
Responsibilities :
· Contributed in creation of test plan for RX Interface
· Took over existing environment and enhanced the same.
· Created functional tests and worked on coverage closure.

SystemVerilogUVMInterlakenVMM

Connexion semiconductors pvt. ltd.,

VLSI Verification Engineer

Feb 2011 – Feb 2012 · 1 yr · Bangalore

2: Verification of Statistic Interface block
Tool used: VCS.
Methodology: VMM
Responsibilities:
Verified Statistic Interface Block.
Written and executed test cases to verify ingress and egress memory.
Written and executed test cases to verify ingress and egress update.
1: 10 Gigabit Ethernet MAC (In-house)
Tools used: VCS.
Methodology: VMM.
Description: Involved in development of Verification environment for Xilinx Ethernet IP. Responsible for writing test cases in VMM to verify functionality of Xilinx Ethernet IP.
Responsibilities: Testing of Configuration Registers and Statistic Counters of Management Interface Block.
Prepared Verification document.
Developed Test bench Components of Management Interface Block.
Written test cases to verify Configuration registers and Statistic Counters.