Hemant Saxena — Director of Engineering

Projects/Protocols :- * Working on UCIe and latest DRAM (LPDDR, GDDR & HBM) VIPs * Worked on Hyperflash Transactor (Verilog RTL Coding) * Worked on EMMC/SD/SDIO/UHS2 VIPs & Testsuites (System Verilog - UVM) * Worked on Interlaken VIP (System Verilog) * Worked on PCIe Gen3/Gen2/Gen1 VIP (Verilog BFM & System Verilog Wrapper) Role/Responsibilities :- * Managing memory and UCIe TS VIP products. * Key BFM’s features implementation in System Verilog and Verilog. * BFM’s Architecture design and FSM implementations. * Worked on Checkers, Scoreboarding, Testbenches/Environments creation, Callback support, Exception mechanism etc. * Code maintenance, Bug fixing and Simprofiling for controlling memory leakage and better time performance. * Worked on Functional Coverage and constraints based System Randomization for configuration, transaction and other data classes. * Worked on Error Exception mechanisms. * Worked on Sequences/Test Cases in UVM/OVM. * Worked on Compliance Test Cases in Verilog. * Worked on Test Suite RAL model. * Integration of VIPs with IIPs. * Prepared Test Plans, Coverage Plans, Checker Plans & Design Documents. * Customer interaction for the Product’s Evaluations, Integration/Deployment and Support Cases.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in Functional Verification and VIP development.

Location: West Delhi, Delhi, India

Experience: 15 yrs 3 mos