Deepthi Jana — CEO
•9+ years of industry experience in ASIC physical implementation, place and route flows. •Practical experience with P&R tools: Fusion Compiler, Design Compiler, ICC2, StarRC, PrimeTime, ARChitect, VCLP, Redhawk, Spyglass, Fishtail, Metaware Debugger, ZeBu and TestMax Manager. •Hands on experience on Flooplanning, fixing the timing issues, improving the utilization by reducing the congestion. •Worked on different Low Power Designs using the techniques: Multi voltage, Adaptive body biasing, XOR Self-Gating, Multi Voltage threshold, Clock gating. •Knowledge of standard data file formats: Verilog, LEF, DEF, SDF, SDC, SPEF, LIB, UPF, DS. •Scripting and programming skills: TCL and Unix shell.
Stackforce AI infers this person is a Physical Design Engineer specializing in ASIC and low-power design in the semiconductor industry.
Location: Hyderabad, Telangana, India
Experience: 8 yrs 9 mos
Skills
- Physical Design
- Low-power Design
Career Highlights
- Over 9 years of experience in ASIC physical design.
- Expertise in low-power design techniques.
- Proficient in multiple P&R tools and methodologies.
Work Experience
Qualcomm
Physical Design Lead Engineer (9 mos)
Synopsys Inc
Physical Design, Staff Engineer (8 yrs)
MosChip Institute of Silicon Systems (M-ISS)
Physical Design Trainee (5 mos)
Education
Advanced PG at Indian Institute of Science (IISc)
Master's degree at Birla Institute of Technology and Science, Pilani
Bachelor's degree at J.B.Institute of Engineering and Technology, Hyderabad
Board of Intermediate Education at Narayana college, Hyderabad
Secondary school certificate at St. Ann's high school, Peddapalli, Karimnagar
