Jan 2018 – Jan 2021 · 3 yrs

• Responsibilities:
• ==========
• Responsible for project/milestone delivery of small/mid/large sized projects for the customer's multiple SOC/IP product life cycles.
• Managing the relationship, looking at opportunities for growth, providing governance for the delivery and being the point of escalation for any issues with the engagement.
• Ensuring that projects are staffed and tracked appropriately and confirm to the customer’s development flow/methodology.
• Propose projects for process improvement, technical enhancements, and cost savings efforts.
• Developing SOWs and project RFP engagement proposals and detailed engagement plans and schedules.
• Working with the senior engineering leadership in defining long-term organizational strategies and road maps and driving the implementation.
• Manage the technical integrations and team partnership with Recruitment, HR and Finance teams.
• Mentoring and coaching the key personnel, assisting in the execution of duties upon request, and readying these key personnel for the next higher role.
• Adapting to customer's business priorities and policies in order to achieve overall program objectives in a collaborative work setup.
• Identify and oversee the training plan for the new joiners and enable them in productive roles in the project.

Jan 2017 – Dec 2017 · 11 mos

• Lead Manager handling the Front-end Technical execution and delivery of state of the art IPs and IP subsystems for current generation SOCs . Handling both design and verification schedule planning, tracking, final deliverable management and people management.

Dec 2015 – Dec 2016 · 1 yr

• Leading a team of verification engineers on the development of next generation Passive Optical Network products (GPON/EPON), Optical Line Termination (OLT) and Optical Network Termination (ONT).

May 2015 – Nov 2015 · 6 mos

• CPU verification lead;
• Verification lead for processor HW debug features meant for software co-development and post silicon debug for next generation X86 and ARM-V8 architecture.
• Includes both self hosted and external debug mode verification.
• Functional tests in ARM Assembly language (v8.2 ISA).
• SV for Assertions and Cover group definitions.
• Regression setup and triage.

Apr 2013 – Apr 2015 · 2 yrs

• Verification Lead;
• Involved from Concept to Tape-out flow process related to a server SOC based on ARM 64 bit processors.
• Handled total verification ownership of some of the sub-system IPs such as SATA, DMA controller, Crypto, Power management in AXI fabric interconnect (ACE-LITE, AXI4, AHB, APB).
• Detailed verification planning, milestone metrics definition, technical guidance for randomization, coverage and regressions/triage.
• Hands-on bringing up verification infrastructure (UVM based) at SOC level, connecting verification components (VIPs) and test coding, coverage.
• Verification emphasis to data and control path verification, stress testing of various masters attached to AXI fabric.
• Power management features verification of various processor power gating/clock gating modes.
• Crypto control processor sub system – Validation of AES, SHA, ECC, RSA Algorithms.
• Mentored junior engineers and contractors for work flow enablement (peak size – 8) and status tracking.
• Handled SOC Gate-level (zero-delay) simulations on milestone Netlists.
• Handled SOC level meta-stable functional simulations for the ownership blocks.
• Handled Post silicon functional bring-up and support for platform silicon/compliance tests.
• Involved in Status reporting, executive summary update and risk management/contingency planning for the ownership blocks.

Aug 2009 – Mar 2013 · 3 yrs 7 mos

• Verification Lead;
• Verification ownership of chip level cycle accurate functional simulations, meant to be run in post silicon ATE, across multiple packages, variants and projects.
• Developed TB infra for verification of Functional/Timing/Reset determinism (Perl Automated Verilog code generation).
• Setup regressions (directed and random tests) and error signature debug/triage.
• Successfully enabled first silicon at sort/package level qualifications with minimal turn-around.
• Involved in status reporting, executive summary update and risk management/contingency planning.

Apr 2001 – Aug 2009 · 8 yrs 4 mos · Bangalore, India

• Worked in various ASIC/SOC/FPGA verification projects in different roles.

Oct 1992 – Jun 1999 · 6 yrs 8 mos · Durgapur, WB

• Handled various positions in industrial control systems, programmable logic controllers and CNC machines programming.

Nov 1991 – Oct 1992 · 11 mos · Chennai, TN

• Worked as an Apprentice trainee at IIT Madras