Vijaya Kirti Gupta

Director of Engineering

Bengaluru, Karnataka, India20 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

20 years of ASIC verification expertise
Led high-performance global teams
Committed to quality and exceeding expectations

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in ASIC and SoC design.

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Skills

Core Skills

Functional Verification

Other Skills

Automotive Functional Safety (FuSa)DebuggingApplication-Specific Integrated Circuits (ASIC)CSystem on a Chip (SoC)Field-Programmable Gate Arrays (FPGA)VHDLRTL DesignVery-Large-Scale Integration (VLSI)PerlUSBUniversal Verification Methodology (UVM)

About

With 20 years of extensive experience in spearheading ASIC verification projects from initial requirements to production-test generation, I have honed my skills in collaborating with global teams and leading high-performance teams. My expertise encompasses testbench architecture and design in Verilog/System Verilog based on UVM, comprehensive test plan development, RTL and Gate-level simulation, and ensuring thorough coverage closure. Known for my enthusiasm and unwavering commitment to quality, I am dedicated to exceeding expectations and delivering exceptional results.

Experience

20 yrs 1 mo

Total Experience

5 yrs

Average Tenure

6 yrs 4 mos

Current Experience

Samsung semiconductor

2 roles

Director

Promoted

Mar 2024 – Present · 2 yrs 2 mos

Functional VerificationAutomotive Functional Safety (FuSa)

Associate Director & Head of Part

Dec 2019 – Feb 2024 · 4 yrs 2 mos

Amd

Member Of Technical Staff

Dec 2016 – Dec 2019 · 3 yrs · Greater Hyderabad Area

Redpine signals

4 roles

Manager (Verification)

May 2015 – Dec 2016 · 1 yr 7 mos

Responsible for complete verification (from testbench achitecture, testplan creation to Gate level testing) of Multi-processor based chip supporting various Wireless and Interface Protocols

Team Lead

Jan 2013 – Apr 2015 · 2 yrs 3 mos

Successfully completely Verification of first 40nm Test Chip having dual processors supporting various Wireless and Interface Protocols
Successfully upgraded SoC Verification Environment to UVM based testbench support various interface and wireless protocols with a team size of 5 people. The 1st verison was up and running in record of 3months.

Lead Engineer

Promoted

Jul 2009 – Dec 2012 · 3 yrs 5 mos

Responsible for Complete Verification of Redpine Signals RS9113 Chip supporting various Wireless and Bus Protocols
Responsible for design, integration and verification of various features of RS9333 Chip

Design Engineer

Nov 2006 – Jun 2009 · 2 yrs 7 mos

Responsible for USB IP testing and implementation of USB host Model in Verilog and System Verilog
Design and Verification of Flow Control Module for PCIE–AHB Bridge

Indian institute of technology, kanpur

Project Associate, National Wind Tunnel Factility

Aug 2003 – Jul 2004 · 11 mos · Indian Institue of Technology, Kanpur

Development and implementation of Virtual Instruments in LabVIEW 6.1 for Wind Tunnel Facility. Client: Arial Delivery Research & Development Establishment, DRDO, Agra
Responsible for upgrade and development of Flight Data Acquisition System for HANSA-3 Trainer Aircraft, owned by Aerospace Engineer Dept., I. I. T. Kanpur