Sahadevan A K

CEO

Bengaluru, Karnataka, India27 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in SOC Integration and Physical Design.
  • Managed over 15 tapeouts from 350 nm to 6 nm.
  • Proven track record in team building and mentoring.
Stackforce AI infers this person is a Semiconductor Design Expert with a focus on SOC and Memory Architecture.

Contact

Skills

Core Skills

Soc IntegrationProject ManagementPhysical DesignMemory Design

Other Skills

SOC constructionChip FloorplanPhysical Design VerificationChip finishing and Sign-offMentoringTape-outJobdeck reviewFloorplanC4 ArraysChip constructionPhysical VerificationSign-off checksDesign of Standalone DRAM ChipsSDRAM/SRAM ChipsCalibre

About

Expertise in Chip design (CPU & Memory) Proven Project Management and Team Management Skills Experience in Building teams from scratch and mentoring new recruits Worked with teams across the globe and with multiple foundries Handled 15+ tapeouts of designs ranging from 350 nm down to 6 nm Resource management/Vendor management experience Third-Party IPs : Delivery tracking and QC for SOC integration Experience in working with teams located at different geographical locations and various functions. Foundry, IPs, Package, Assembly, Technology, CAD, PE and PD Hands-on expertise SOC Integration & Physical Design Circuit/Layout Design Chip Floorplan/Bump planning fullchip construction, Physical verification, Chip finishing and Sign-off, Physical Design/Block PnR, Timing closure and electrical checks Functional verification Memory architecture and array configuration (SDRAM/SRAM) Redundancy schemes

Experience

27 yrs 10 mos
Total Experience
8 yrs 8 mos
Average Tenure
2 yrs
Current Experience

Qualcomm

SOC Program Mangement - Staff

May 2024Present · 2 yrs · Bengaluru, Karnataka, India · On-site

SOC constructionChip FloorplanPhysical Design VerificationChip finishing and Sign-offProject ManagementMentoring+1

Amd

Senior Manager, Design Engineering

Apr 2009May 2024 · 15 yrs 1 mo · Bangalore

  • Physical Design, SOC Integration, Tape-out, Jobdeck review, Floorplan, C4 Arrays, RDL, Chip construction, Physical Verification and sign-off checks.
Physical DesignSOC IntegrationTape-outJobdeck reviewFloorplanC4 Arrays+3

Edison semiconductor/elpida memory

Lead Engineer

Jan 2006Jan 2009 · 3 yrs

  • Design of Standalone DRAM Chips for Elpida Memory, Japan
Design of Standalone DRAM ChipsMemory Design

Alliance semiconductor

Lead

Apr 1998Apr 2006 · 8 yrs · Bangalore

  • Memory Design: SDRAM/SRAM Chips
Memory DesignSDRAM/SRAM Chips

Education

Mahatma Gandhi University ( MACE Kothamangalam)

Bachelor's degree

St. Berchmans College, Kerala

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