Skills

• System Verilog
• Universal Verification Methodology (uvm)
• Digital Ip Verification

Career Highlights

• Lead Engineer with expertise in System Verilog and UVM.
• Experience in digital IP verification across multiple protocols.
• Strong background in SoC design and verification methodologies.

Work Experience

Education

Master's Degree at International Institute of Information Technology Bangalore

Bachelor's Degree at Medicaps Institute of Technology & Mgmt.

High School at Standard Public School, Indore