Paripati Yeshwanth

Software Engineer

Bengaluru, Karnataka, India4 yrs 11 mos experience

Highly Stable

Key Highlights

Experienced in VLSI design and emulation.
Proficient in multiple verification methodologies.
Strong background in silicon design engineering.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in silicon design and verification methodologies.

Contact

Skills

Other Skills

VCSShell ScriptingTCLZebuVery-Large-Scale Integration (VLSI)VerilogUniversal Verification Methodology (UVM)SystemVerilog

About

VLSI Enthusiast

Experience

4 yrs 11 mos

Total Experience

2 yrs

Average Tenure

11 mos

Current Experience

Amd

Sr. Silicon Design Engineer

Jul 2025 – Present · 10 mos · Bengaluru, Karnataka, India

Synopsys inc

2 roles

Sr. Applications Engineer

Promoted

Dec 2024 – Jul 2025 · 7 mos · Bengaluru, Karnataka, India

Applications Engineer

Feb 2022 – Nov 2024 · 2 yrs 9 mos · Bengaluru, Karnataka, India

Maven silicon

Trainee

Jun 2021 – Feb 2022 · 8 mos · Bengaluru, Karnataka, India

Signals & systems india pvt ltd

Intern

Jul 2018 – Aug 2018 · 1 mo · Chennai, Tamil Nadu, India

Education

BITS Pilani Work Integrated Learning Programmes

Master of Technology - MTech — Microelectronics

Jan 2023 – Jan 2025

SRM IST Chennai

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2016 – Jan 2020

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