Avirup Mandal

Product Engineer

Noida, Uttar Pradesh, India14 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in RTL design and debugging.
Strong background in VLSI and EDA tools.
Proven track record in synthesis and equivalence checking.

Stackforce AI infers this person is a VLSI and EDA expert with strong RTL design capabilities.

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Skills

Core Skills

Rtl IntegrationSynthesisFe SynthesisConformalDebuggingEquivalence CheckingRtl Designing

Other Skills

Netlist quality checkTiming constraint qualityPowerArtistIP quality checkParsingElaborationHigh Level optimizationDatapath OptimizationDebugging pre and post synthesis simulationCreating HDL designs/testcasesVHDLVerilogSystem VerilogC programmingScripting

Experience

14 yrs 5 mos

Total Experience

3 yrs 10 mos

Average Tenure

2 yrs 11 mos

Current Experience

Cadence design systems

Sr principal product engineer

Jun 2023 – Present · 2 yrs 11 mos · Noida, Uttar Pradesh, India · Hybrid

Intel corporation

2 roles

SoC Design Engineer

Jan 2021 – Jun 2023 · 2 yrs 5 mos

As FE IP TFM Engineer supporting RTL integration(Coretools), Synthesis(FC), Conformal(LEC), Netlist quality check(Caliber), Timing constraint quality(Fishtail), Jasper, PowerArtist and IP quality check(IPQC) before hand-off to SOC.
Involved lot FE Methodology items' execution and support for IPs quality.

RTL integrationSynthesisConformalNetlist quality checkTiming constraint qualityPowerArtist+1

Staff Engineer

Dec 2019 – Dec 2020 · 1 yr

As CAD engineer developed and deployed FE synthesis(FC, Genus), conformal(LEC), Timing Constraint quality(Fishtail) flows.

FE synthesisConformalTiming Constraint quality

Cadence design systems

2 roles

LMTS

Jul 2016 – Nov 2019 · 3 yrs 4 mos

Analyzing and debugging Customer designs(SV,VHDL-2008,MIXED HDL) for Parsing, Elaboration, High Level optimization, Datapath Optimization etc. related issues.
Provide instant workaround(Rewrite RTL/ Proper tool's usage) to Customer.
Provide RTL workaround to improve Timing, Area of Customer's design.
Equivalence checking(LEC) of different RTLs, netlists generated by Cadence synthesis tool(GENUS).
Debugging pre and post synthesis simulation mismatch related failure(IES).
Presenting new RTL features to internal team before supporting those in a best way.
Creating Testplan for proper EDA tools' testing after new HDL or new architectural flow related feature support.

DebuggingParsingElaborationHigh Level optimizationDatapath OptimizationEquivalence checking+1

SMTS

Jan 2015 – Jun 2016 · 1 yr 5 mos

Analyzing and debugging Customer RTL designs(SV,VHDL etc.) for Parsing, Elaboration, optimization related issues.
Equivalence checking of different RTLs, netlists generated by Cadence synthesis tool.
Creating different kind of HDL(Verilog,SV,VHDL,VHDL-2008,Mixed) designs/testcases to check behavior, performance of Cadence EDA tools(RC/Genus/LEC/NCV).

DebuggingEquivalence checkingCreating HDL designs/testcases

Interra systems

2 roles

Design Engineer

Aug 2011 – Dec 2014 · 3 yrs 4 mos · Noida Area, India

Beacon's RTL designing in VHDL,VHDL-2008,Verilog,System Verilog and Mixed HDL/HVL languages.

RTL designingVHDLVerilogSystem Verilog

Application Engineer

Aug 2011 – Dec 2014 · 3 yrs 4 mos · Noida Area, India

Playing an active role in between Customer and R&D team for debugging customer issues on RTL design.
Writing expected application on C language using different APIs on Interra EDA tools(Jaguar/Cheetah).
Automate Interra regression suits through c-shell, perl and tcl scripting.

DebuggingC programmingScripting