Jun 2022 – Apr 2024 · 1 yr 10 mos

• Domain knowledge: Worked on multiple projects in System-on-Chip (SoC) verification on Automotive and Consumer Electronics(Mobile phones and IOT devices)
• Experience in end-to-end SOC verification project life cycle, which includes, testbench strategies, TB development , simulation debugs using System Verilog/UVM and ARM C based verification environment.
• Led verification planning activities, including requirement analysis, test scenario definition ,test plan creation, verification environment strategy, traceability matrix document resulting in a 25% increase in test coverage completeness.
• Designed and implemented advanced SV and UVM testbenches for complex designs, achieving a 40% reduction in bug escapes to subsequent verification stages.
• Implemented SystemVerilog Assertions (SVA) to define design properties and verify correct behavior in RTL designs.
• Implemented functional coverage techniques, leading to a 50% improvement in functional coverage closure and a 15% reduction in simulation debug time.
• Certified Functional Safety Engineer –Level 1 from TUV SUD, South Asia for successfully completing the Functional Safety Certification Program(FSCP) based on ISO 26262:2018(2nd Edition), Road Vehicles
• Exposure to fault injection simulations, Fault Tree Analysis(FTA), Dependent Failure Analysis (DFA), DFMEA, FMEDA for automotive functional safety chips according to ISO-26262 standards.
• Good exposure to ARM Cortex R5, R4 , M4 & Cortex A32 processor in SOC verification.
• Expertise in AMBA(APB, AHB, AXI) bus protocol, I2C, SPI, UART.
• Hands on experience in GLS setup, analyzing the critical timing violations and its associated debugs.
• Cross-functional Collaboration with the ATE(Automated Test Equipment) validation team to enhance DV tests/testbenches for validation purposes.
• Led and managed ASIC team with team size being 3 to 7, to drive SoC verification activities and ensured delivery within timelines.

Jun 2019 – Jun 2022 · 3 yrs

• Hands on Experience in SOC Verification involving ARM processor and functional safety mechanisms for automotive chips.
• Coded testbench components from scartch using SV/UVM.
• Integrated the block level/IP level UVM based verification environment into SOC level environment.
• Coded C test cases and integrated the C tests with UVM based environment for SOC design verification.
• Implemented assertions using System Verilog Assertions (SVA) to define design properties and verify correct behavior in RTL designs.
• Ran Gate Level Simulations (GLS) and checked the critical timing paths, reported timing violations and X propagation issues in system design.
• Designed and implemented functional coverage models to track the completeness of verification test suites.Implemented covergroups, coverpoints, and cross coverage to monitor the state space of the design and identify untested scenarios.
• Conducted system-level and block-level debugging to identify and resolve critical issues in digital designs.

Oct 2018 – Jun 2019 · 8 mos

• Worked on multiple projects in IP and SOC verification involving ARM processors and AMBA(AHB,APB,AXI4) protocols.
• Developed testbench components using UVM from scratch and also reusing the existing verification environment.
• Coded UVM based sequences ,constraint random driven tests and generate functional coverage report
• Coded system verilog assertions to verify the correctness of RTL design.
• Debugged the failing tests in functional simulations and gate level simulations(GLS).
• Bugs reported are meticulously documented, providing details like the nature of the issue, steps to reproduce them etc

Feb 2017 – Oct 2018 · 1 yr 8 mos · Bengaluru, Karnataka, India · On-site

• IP verification of AXI4 Verification IP using SV/UVM, coded testbench components from scratch.
• Conducted connectivity checks/Port analysis for a automotive IC verifying the connectivity and communication between various components or devices in a system, ensuring that they can properly exchange data or signals as intended.
• Checked for X propagation issues for a SOC by running gate level simulations
• Debugged failing test cases and reported the error.
• Perform regression management to ensure coverage goals are met.