Himanshu Yadav

Software Engineer

New Delhi, Delhi, India0 mo experience

Key Highlights

Expert in Physical Design and Static Timing Analysis.
Proven track record in optimizing power grid architectures.
Strong background in ASIC design and digital electronics.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Static Timing Analysis.

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Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Synopsys PrimetimeSynopsys ICC-IIRedhawkSynopsys ICC2Ansys RedHawkTCL scriptingCTBFCTIV cellsPerlDigital Design with FPGADigital IC DesignDigital ElectronicsIntel Quartus PrimeModelSimVerilog HDL

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Mediatek

Physical Design Engineer

Sep 2025 – Present · 8 mos · Bengaluru · On-site

Synopsys PrimetimeSynopsys ICC-IIRedhawkPhysical DesignStatic Timing Analysis

Stmicroelectronics

Physical Design and Signoff

Jul 2024 – Jun 2025 · 11 mos · Noida · On-site

Optimized power grid architecture for a 72 MHz SoC design with 84K+ standard cells using Synopsys ICC2 and Ansys RedHawk, reducing IR drop and improving power integrity.
Enhanced floorplan TCL scripts and conducted post-layout STA to assess congestion and timing impact of power grid modifications.
Analyzed key optics using CTBF and CTIV cells to analyze their isolated and combined effects on ASIC like global/local skew, clock power, congestion, crosstalk, EM/IR drop, and timing closure.

Synopsys ICC2Ansys RedHawkTCL scriptingStatic Timing AnalysisCTBFCTIV cells+1