GL Krishna Reddy Tadi

Software Engineer

Hyderabad, Telangana, India13 yrs 5 mos experience

Most Likely To SwitchAI Enabled

Key Highlights

7 years of expertise in IP and SoC level verification.
Proven track record in developing robust verification plans.
Specialized in building efficient testbenches and debugging.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in IP and SoC verification.

Contact

Skills

Core Skills

Verification MethodologiesProtocolsSoc Verification

Other Skills

UVMTestbench architectureVerification planFunctional SafetyAXII3CVCSCANDesign architectureRALDebuggingTestcase failure fixesCoverage improvementMentoringGuiding juniors

About

I am an experienced Verification Engineer with 7 years of expertise in both IP and SoC level verification. I have a deep understanding of SystemVerilog and UVM methodology, with a proven track record in developing and executing robust verification plans. My core experience includes working with a variety of protocols, including USB, SPI, AMBA (APB, AXI-lite), CAN, I3C, and I2C, ensuring high-quality deliverables in complex projects. I specialize in building efficient testbenches, performing thorough coverage analysis, and debugging complex verification challenges. I am well-versed in industry-leading EDA tools like Cadence Xcelium and Synopsys VCS, allowing me to contribute effectively to verification environments. Key skills include: Verification Methodologies: UVM, OVM Programming Languages: Verilog, SystemVerilog, C Protocols: USB, SPI, AMBA (APB, AXI-lite), CAN, I3C, I2C Tools & Environments: Cadence Xcelium, Synopsys VCS With a passion for problem-solving and a focus on high-quality verification, I continuously strive to optimize verification processes and ensure reliable product delivery.

Experience

13 yrs 5 mos

Total Experience

1 yr 11 mos

Average Tenure

4 yrs 4 mos

Current Experience

Amd

2 roles

Senior Silicon Design Engineer

Promoted

Apr 2024 – Present · 2 yrs 2 mos · Hyderabad, Telangana, India · Hybrid

Project12:(Aug 2025 - present)
Working on axi-xspi
Developed uvm test bench from scratch using xam uvc to verify hyperbus functionality
Integrated Ral env using xam uvc in testbench
Made Verification plan and testplan for hyperbus functionality
developing test cases and sequences to verify hyperbus functionality
Project11:(May 2025 - July 2025)
Worked on axi-gpio for functional safety
Developed uvm test cases to check safety measure of IP
Modififed existing testbench and updated to support VCS flow
worked on VCS merged coverage reports on VIPER(viper is a framework which take care of Regression and generate reports)
Made testplan, verification plan, coverage plan and other functional safety verification documents
Project 10: (March 2025 - April 2025)
Worked on CANFD
understand the existing IP working
worked with Designers to bring up Design Architecture for Multichannel CANFD(existing IP is single channel)
Project9:(Dec 2024 - Feb 2025)
Worked on axi-gpio
Developed uvm testbench bench from scratch which is for a legacy IP
integrated Ral agent and xam uvc in testbench
written cover groups for axi gpio
Made testplan, verification plan, coverage plan and other verification documents
project8:(May 2024 - Nov 2024)
worked on I3C(Target)
Developed Testbench from scratch.
Verified Registers using RAL
Verified I3c Target, which supports for only SDR mode
Implemented checkers for check Data.
Verified interrupts.
Verified all controller response codes.
Verified PEC feature
Verified IBI functionality(with and with out payloads)
Verified Hot Join functionality
verified secondary controller functionality
implemented error injection test-cases(start, stop,parity bit,T bit, pec byte corruption)

UVMTestbench architectureVerification planFunctional SafetyAXII3C+2

Silicon Design Engineer 2

Feb 2022 – Apr 2024 · 2 yrs 2 mos · Hyderabad, Telangana, India · Hybrid

project7: (MAR 2023 to APRIL 2024)
worked on I3C(controller)
Developed Testbench from scratch.
Verified Registers using RAL
Verified I3c controller, which supports for legacy i2c and only SDR mode
Implemented checkers for check Data.
Implemented checkers to detect bus release conditions, start and stop conditions.
Verified interrupts.
Verified all controller response codes.
Verified PEC feature
Verified multi Bus functionality (connected multiple I3C and I2C targets on bus and performed back to back writes and reads with Reated start and stop)
Verified IBI functionality(with and with out payloads)
Verified Hot Join functionality
project6:(Sept 2022 to FEB 2023)
Worked on CAN protocol
Verified Registers using RAL
Verified interrupts.
Verified ECC feature in can protocol
project5:(May 2022 to AUG 2022)
worked on AXI-EPU
Verified Axi-EPU registers using RAL

UVMRALI3CCANAXIVerification Methodologies+1

Xilinx

Design Engineer 2

Jan 2022 – Feb 2022 · 1 mo · Hyderabad, Telangana, India

xilinx has merged in to AMD from Feb 14th 2022
Project4:(Jan 2022 to April 2022)
worked on AXI-Firewall
Test Case debugging
Fixed TB issues and brought coverage near to 99℅

DebuggingTestcase failure fixesCoverage improvementVerification Methodologies

Cerium systems

Engineer

Dec 2020 – Jan 2022 · 1 yr 1 mo · Hyderabad, Telangana, India

worked on soc verification(INTEL client)
Project3:
Verified clock and reset functionality
Written sv-uvm and c testcases
Developed assertions
Developed checkers for connectivity checks
worked on code coverage(toggle coverage)
Ran daily regressions
Debugged failure testcase
Mentored and trained team members

SoC verificationMentoringGuiding juniorsSoC Verification

Sasic technologies private limited

Verification Engineer

Dec 2017 – Dec 2020 · 3 yrs · Bengaluru, Karnataka, India · On-site

From April 2020, coqube acquired sasic
project2:
worked on Register verification using RAL(ADI client)
updated sv model using yoda when ever RTL updates
Ran regressions
Debugged failure test case
updated test case/sequence/constraints
project1:
worked on usb protocol - link layer(INTEL client)
Ran regressions
Debugged failure test case
updated test case/sequence/constraints

RALUSB3.2DebuggingProtocols

Nations pride energy systems private limited

Senior Design Engineer

Sep 2014 – Jul 2017 · 2 yrs 10 mos

Domain: solar

Marwadi university

Assistant Professor

Jun 2014 – Sep 2014 · 3 mos

Sai madhavi institute of science and technology

Assistant Professor

Jun 2011 – Jun 2012 · 1 yr

United enterprises

Field Engineer

Jun 2010 – May 2011 · 11 mos

Education

Vellore Institute of Technology

Master of Technology - MTech — Power Electronics and Drives

Jul 2012 – May 2014

Aditya University

Bachelor of Technology - BTech — Electrical and Electronics Engineering

Sep 2006 – Apr 2010

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