Dheeraj Nomannagari

CTO

Hyderabad, Telangana, India18 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC and FPGA design and verification.
  • Proficient in SystemVerilog and UVM methodologies.
  • Extensive experience in SoC verification projects.
Stackforce AI infers this person is a specialist in semiconductor design and verification within the VLSI industry.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationAsic

Other Skills

SystemVerilogUniversal Verification Methodology (UVM)FPGAVerilogVLSIUSBDebuggingVHDLAMBA AHBXilinxIntegrated Circuit DesignEDAVery-Large-Scale Integration (VLSI)Open Verification MethodologyModelSim

Experience

18 yrs 5 mos
Total Experience
2 yrs 3 mos
Average Tenure
7 yrs 9 mos
Current Experience

Amd

2 roles

Senior Member Of Technical Staff

Promoted

Jul 2022 – Present · 3 yrs 11 mos

SystemVerilogUniversal Verification Methodology (UVM)ASICFPGAFunctional VerificationVerilog+18

MTS Design Engineer

Aug 2018 – Jun 2022 · 3 yrs 10 mos

Xilinx

Consultant through Sivaltech Inc

Sep 2017 – Jul 2018 · 10 mos · Hyderabad Area, India

Qualcomm

Consultant through Mirafra Inc

Feb 2017 – Jul 2017 · 5 mos · United States

Imagination technologies

Hardware Design Engineer (ASIC/SOC Verification)

Aug 2013 – Jan 2017 · 3 yrs 5 mos

  • Involves SoC Verification using UVM,System Verilog, C languages
UVMSystem VerilogC languagesFunctional VerificationASIC

Posedge (acquired by imagination technologies)

ASIC Verification Engineer

Oct 2012 – Jul 2013 · 9 mos · Hyderabad Area, India

Wipro technologies

Senior Project Engineer

Jul 2011 – Oct 2012 · 1 yr 3 mos · Hyderabad Area, India

  • Service provider to Freescale Semiconductors and it involves the verification of SoC

Moschip semiconductor

ASIC Design Engineer (Verification of IP's and SoC)

Jul 2008 – Jun 2011 · 2 yrs 11 mos · Hyderabad Area, India

  • IP Verification of serial port IP, USB 3.0 (which involves xHCI), and some other propietary protocols verification and SoC Verification

Acl pvt ltd

Project Trainee (Internship as a part of Master Degree Course)

Nov 2006 – Dec 2007 · 1 yr 1 mo · Hyderabad

  • RTL Coding(VHDL), ARINC and Milstd1553 Protocols implementing on FPGA
IP VerificationUSB 3.0SoC VerificationFunctional VerificationASIC

Education

Manipal School of Information Sciences

M.S — VLSI CAD

JNTU Anantapur

B-tech

Loyola Junior College, Alwal, Secunderabad.

Intermediate (12th Standard)

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