Kirtesh Tiwari

Co-Founder

Bengaluru, Karnataka, India14 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 15 years in VLSI Physical Design.
Expert in advanced semiconductor technologies.
Contributed to multiple tape-outs across cutting-edge nodes.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in VLSI Physical Design.

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Skills

Core Skills

Physical DesignSemiconductor EngineeringStatic Timing AnalysisRtl To Gdsii

Other Skills

Clock DistributionProblem SolvingCTSLECFloorplanningPlace & RouteCustomer InteractionFlow DevelopmentDesign Suite PreparationRegression AnalysisSTAVerilogLVSDRCRouting

About

With over 15 years of experience in VLSI Physical Design, I have had the privilege of working on some of the most advanced semiconductor technologies in the industry—from 3nm and 5nm nodes to legacy nodes like 180nm. My journey has been driven by a passion for solving complex design challenges and delivering optimized solutions that meet stringent performance, power, and area (PPA) requirements. I specialize in the complete Netlist-to-GDSII flow, with deep expertise in: ✔ Synthesis, Place & Route, Physical Verification (PV), and Logic Equivalence Check (LEC) ✔ Static Timing Analysis (STA), Clock Tree Synthesis (CTS), IR/EM Analysis, and Low-Power Design ✔ PV and LEC at both Block and Top Level, including Low-Power LEC ✔ Automation and optimization using TCL and Python scripting ✔ Exploring Machine Learning applications in Physical Design Throughout my career, I’ve contributed to multiple tape-outs across cutting-edge nodes like 3nm, 5nm, 7nm, and 10nm, ensuring robust designs for high-performance computing and low-power applications. I thrive in fast-paced environments where innovation and precision go hand in hand. If you’re passionate about semiconductor design, advanced nodes, or automation in VLSI, let’s connect—I’m always excited to share knowledge and explore new ideas.

Experience

14 yrs 11 mos

Total Experience

4 yrs 3 mos

Average Tenure

10 yrs 7 mos

Current Experience

Qualcomm

2 roles

Staff Engineer

Oct 2022 – Present · 3 yrs 7 mos · Bengaluru, Karnataka, India

Clock DistributionPhysical DesignSemiconductor EngineeringProblem SolvingCTSLEC

Lead Engineer Sr

Sep 2017 – Sep 2022 · 5 yrs · Bengaluru, Karnataka, India

Part of High Performance Snapdragon X55 and X60 5G Modem Design Team for mid and premium tier smartphone chip.
Handling and designing modem blocks which includes floor planning, place and route (PNR) and static timing analysis (STA).

Clock DistributionPhysical DesignSemiconductor EngineeringProblem SolvingCTSLEC

Synopsys inc

Lead Physical Design Engineer

Nov 2016 – Sep 2017 · 10 mos · Noida Area, India

Responsibilities include:
1. RTL to GDS|| implementation of various customer blocks.
2. Visit Customer places to resolve their problems and provide explanation to their queries.
3. Lynx flow development for various foundries such as TSMC, USMC etc.
4. Give guidance to team if needed.

Clock DistributionPhysical DesignSemiconductor EngineeringProblem SolvingLEC

Sarva jana hitaya

Founder President

Oct 2015 – Present · 10 yrs 7 mos · Ghāziābād Area, India

My Roles and Responsibilities includes following :
1. Attend all the meetings and after getting inputs from all members come up with the plan.
2. Provide updates on social media and coordinate with other NGOs .
3. List all requirements and supervise all financial activities .
4. Provide initial flow chart and wire frame for website as well as app development.

Mentor graphics

Product Specialist II

Oct 2015 – Nov 2016 · 1 yr 1 mo · noida

working for RTL to GDS|| implementation of customer projects, revalidating and debugging existing product along with the QA, resolving issues & documentation of the existing product.
Responsible for preparing design suites, test cases, execution & analysis of regressions for new features; bug fixing/discovering, working as interface between AEs and R&D, to understand/identify problem, and propose solutions, in Olympus-SOC and Real Time.

Clock DistributionPhysical DesignSemiconductor EngineeringProblem SolvingLEC

Synapse design automation inc.

Senior Engineer & Lead

Oct 2014 – Oct 2015 · 1 yr · Hsinchu County/City, Taiwan · On-site

My responsibility includes
1. Share knowledge with trainees and give them presentation.
2. RTL to GDSII flow including STA and CTS for block as well as full chip level designs.

Clock DistributionPhysical DesignSemiconductor EngineeringProblem SolvingLEC