Dec 2016 – Dec 2020 · 4 yrs · Greater Bengaluru Area

• Verification of complex SerDes features which includes leading multicore verification team from 56G and 112G LR projects.
• Mentoring new team members in HSS verification.
• Responsibility of verification for the various algorithms and features in 112G XSR core.
• Proposed new methodology to verify asynchronous reset v/s statemachines using Functional verification methodology and verified the core accordingly
• Reproduced multiple Lab failures in verification environment and propsed a solution to catch more such issues
• Created scripts to do data-analysis on Equalization algorithms and dataflow tests which was recognized across the teams

Dec 2016 – Aug 2017 · 8 mos · Bengaluru Area, India

• Verification of complex SerDes Rx algorithms which involves coding the verification scenarios, checkers, monitors for the algorithms.
• Mentoring Junior team Members in verification.

Jul 2015 – Dec 2016 · 1 yr 5 mos · Bengaluru Area, India

• Multi-protocol Test Chip:
• Verification of Multi protocol Test chip which includes developing VPLAN, bringing up test-chip environment and driving the task to the completion on time. Also Mentoring people to setup Formal verification Apps for the core.
• DIGIRF Controller:
• Bringing up and Architect of UVM verification environment for the DIGIRF core and responsible for the Register verification using UVM_REG package.
• UPHY_UDP_PHY:
• Architect of verification environment which includes planning and development of verification Environment.
• Analysis of Code and Functional coverages for USB TYPE-C using formal and VManager.
• AMS simulations and debug.
• Connectivity and Registers verification by using Jaspergold.

Jul 2011 – Jun 2015 · 3 yrs 11 mos · Bengaluru Area, India

• 14nm – PCIE-PHY core verification:
• Verification of PLL, RX, and TX registers using UVM_REG package.
• Verification of the Decision Feedback Equalizer part of the core – H-coefficients.
• Development of Channel model for the core. • Analysis of Register Coverage.
• 32nm – HSS 28G Low Power Core Verification:
• Verification of Macro tests and automatic checkers development to check Analog Digital Boundary.
• Verification of the Decision Feedback Equalizer part of the core – Developed UVC's and test cases for the Variable Gain Amplifier, PRBS7offset and Integrator calibrations part of the core.
• Code/Functional Coverage Analysis for RX portion of the core.
• 32nm – HSS 15G Back Plane Core Verification:
• Developed and verified the complete registers suite using RGM package.
• Responsible for complete Channel Model Setup in the Environment.
• Responsible for the complete successful verification of PLL.
• Developed and Verified SAS protocol style for the Core.
• Responsible for the complete AMS model setup and its verification in the environment.
• Verification of Eye metrics (wave form Mode).
• Developed Regression results collection script and responsible for complete regression management between 10 people.
• Development and Analysis of Functional Coverage, Code coverage (Expression, Block, Toggle).
• 32nm – HSS 15G Chip to Chip Core Verification:
• Developed and maintained Test cases on the PLL portion of the core.
• Received praise for the work for setting up unified AMS model (TX/RX/PLL) setup for
• the core.
• Functional Coverage analysis of the Core.
• 32nm – PCIE3phy Verification:
• Development and verification of Eye metrics for the first time in IBM in Verification environment.
• Developed and maintained better Regression system.
• Involved in development and analysis of Functional Coverage.

Jan 2011 – Jul 2011 · 6 mos · Bengaluru Area, India

• Setting up AMS models and Verification for those models (PLL,Rx Tx) for HSS cores
• Scopemode Verification (EYE Metrics) for PCIE3 core
• AMS simulations and debug.
• Coverage Analysis Using IMC and ICCR
• Regressions

Jul 2009 – Dec 2010 · 1 yr 5 mos · Pune Area, India

• Incharge of LAB.
• Installing Cadence tools.