Tanu Ginotra Pruthi

Software Engineer

Delhi, India12 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 8 years of experience in low-power VLSI design.
Successfully completed 10+ tapeouts across various sectors.
Expert in UPF generation and power-related debugging.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on low-power VLSI design.

Contact

Skills

Core Skills

Low-power DesignPower ManagementDigital DesignTiming AnalysisValidation Engineering

Other Skills

UPF generationConformal CLPpower estimationautomationpost-silicon correlationblock-level synthesisconstraints validationECO developmentreporting dashboardsRC extractionautomation scriptsTiming tool validationQA of design toolsStatic Timing AnalysisVerilog

About

Experienced VLSI Design Engineer with over 8 years of expertise primarily in low-power design across advanced technology nodes (4nm to 14nm). Proven track record of completing 10+ successful tapeouts for mobile, compute, and automotive designs. Skilled in UPF generation, debugging power-related issues, PTPX simulation and driving automation for improved execution. Strong technical background in scripting (Perl, Shell, TCL) and working with industry-standard EDA tools (PrimeTime, Design Compiler, Genus). Known for effective collaboration in cross-functional teams environnent and mentoring junior engineers.

Experience

12 yrs 5 mos

Total Experience

3 yrs 2 mos

Average Tenure

6 yrs 9 mos

Current Experience

Amd

2 roles

Member of Technical Staff

Sep 2019 – Present · 6 yrs 8 mos

Member of Technical Staff

Sep 2019 – Present · 6 yrs 8 mos

Qualcomm

Senior Technical Lead

Sep 2019 – Apr 2026 · 6 yrs 7 mos · Noida, Uttar Pradesh, India · On-site

Led UPF generation from scratch, including sanity checks and optimization of isolation, level shifter, and retention cells.
Performed deep debugging of UPF-related issues using Conformal CLP, ensuring high-quality low-power design.
Handled power estimation (Peak Power, RBSC, DDR Ready) for lower technology node projects.
Developed and implemented automation for critical design flows, improving execution efficiency.
Managed post-silicon correlation for power metrics, facilitating smooth coordination between design, validation, and ATE teams.
Provided mentorship to new hires, enhancing their understanding of low-power design processes.

UPF generationConformal CLPpower estimationautomationpost-silicon correlationLow-Power Design+1

Mediatek

Engineer

Jul 2017 – Sep 2019 · 2 yrs 2 mos · Bangalore

Conducted block-level synthesis targeting area, timing, and power optimization.
Validated constraints using CCD, identifying and fixing issues with clock relationships and overriding constraints.
Developed ECOs to resolve setup and hold violations using PrimeTime.
Created and validated asynchronous SDCs and CCF files, ensuring robust design quality.
Automated reporting dashboards using Perl, improving visibility and workflow efficiency.

block-level synthesisconstraints validationECO developmentreporting dashboardsDigital DesignTiming Analysis

Altran india

Engineer

Apr 2016 – Jul 2017 · 1 yr 3 mos · Bangalore

Performed RC extraction and top-level timing analysis, validating inputs for proper linking and annotation.
Automated scripts to streamline extraction and timing analysis processes.
Contributed to successful tapeouts at 14nm and 10nm nodes.

RC extractiontiming analysisautomation scriptsTiming AnalysisDigital Design

Mentor graphics

Product Validation Engineer

Jul 2015 – Nov 2015 · 4 mos · Noida Area, India

Timing tool Optimus : Validation of the test cases. Reviewing all the commands of Optimus, involving working on Timing Reports & scripts.
PNR Flow tools Olympus & Nitro : QA of different designs from the industry for both the tools.

Timing tool validationQA of design toolsValidation Engineering