Sumit Jha

Product Engineer

Bengaluru, Karnataka, India12 yrs 11 mos experience

Key Highlights

Expert in high-performance IP and SoC design.
Delivered Google's first Mobile SoC, Google Tensor.
Extensive experience in power grid design and physical verification.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and SoC development.

Contact

Skills

Core Skills

Physical DesignPower DistributionSocPower Grid DesignPower EstimationAutomation

Other Skills

P&RSynthesisFloorplanningPlace & RouteECO ConvergenceTimingIR ClosureDesign Rule Checking (DRC)Layout Versus Schematic (LVS)PDNShell ScriptingPower ConsumptionLayout VerificationProblem SolvingMentor Graphics

About

Proficiency in Power grid design of high-performance IPs and SoCs. Involved in multiple tapeouts handling end-to-end responsibilites from RTL to GDS. Expertise in pushing PPA and solving complex physical design problems.

Experience

12 yrs 11 mos

Total Experience

2 yrs 8 mos

Average Tenure

2 yrs 2 mos

Current Experience

Google

Senior Silicon Engineer

Apr 2024 – Present · 2 yrs 2 mos · Bengaluru, Karnataka, India · Hybrid

Sifive

Senior Staff Engineer

Apr 2022 – Apr 2024 · 2 yrs

Power DistributionP&RPhysical Design

Google

Silicon Engineer

Dec 2018 – Mar 2022 · 3 yrs 3 mos · Bangalore

Core member of the CPU team that delivered Google's first Mobile SoC "Google Tensor".
Responsible for synthesis, floorplanning, place & route, ECO convergence, timing, IR, and PDV closure for multiple high-performance CPU modules for Google Tensor chips G1, G2 and G3.

Physical DesignSoC

Qualcomm

Senior Engineer

Jan 2017 – Dec 2018 · 1 yr 11 mos

Was Part of Qualcomm global methodology and technology group.
Extensively worked on power grid design, IR drop spec creations and header switch innovations.
Responsible for PDN and PV signoff for multiple premium tier chips.

Power Grid DesignPhysical Design

Nxp semiconductors

2 roles

Senior Physical Design Engineer

Promoted

Apr 2016 – Jan 2017 · 9 mos

Worked on various aspects of physical design like Floorplanning, Power estimation, IR drop analysis and physical verification on multiple C90 parts.
Involved in multiple key strategic initiatives that were deployed across multiple sites.

Physical DesignPower Estimation

Physical Design Engineer

Jun 2013 – Apr 2016 · 2 yrs 10 mos

Physical Design Engineer for Automotive MCU
Worked on multiple projects and a wide range of technologies: 90nm, 55nm
SoC level floorplanning, IR Drop Analysis, Physical Verification, Power Estimation.
TCL/Perl scripting for automation and flow development.

Design Rule Checking (DRC)Layout Versus Schematic (LVS)Physical DesignAutomation