Sandhya P V — Software Engineer
Engineer with experience on SOC & IP Verification . - worked on AXI, AHB Lite , MIPI DSI, I2C. - Test plan / Test case /Test bench development at block level. - Developed RAL model from scratch. - Good knowledge on SVA. - Developed coverage plan and worked on functional coverage. - Have experience in performance verification. - Hardware Description Languages : Verilog and SystemVerilog. - Programming Languages : C - Methodology Expertise : Universal Verification Methodology (UVM). - Scripting Languages : Perl, python. - Simulation Tools : Aldec, VCS. - Operating System : Linux
Stackforce AI infers this person is a VLSI Verification Engineer with expertise in SOC design and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 9 mos
Career Highlights
- Expert in SOC and IP Verification methodologies.
- Proficient in Verilog and SystemVerilog for hardware design.
- Strong background in Universal Verification Methodology (UVM).
Work Experience
Cisco
Hardware Engineer (1 mo)
Career Break
Health and well-being (3 mos)
AMD
Sr.Design Verificaiton Engineer (2 yrs 5 mos)
Senior Silicon Design Engineer (3 yrs 9 mos)
Eximius Design
Design and verification engineer (3 yrs 11 mos)
Education
Bachelors at East Point College Of Engineering And Technology
