Chaithanya Kotagiri

Product Engineer

Bengaluru, Karnataka, India14 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI Physical Design methodologies.
Proficient in static timing analysis and physical verification.
Strong background in Place and Route design.

Stackforce AI infers this person is a VLSI Physical Design Engineer with expertise in semiconductor design.

Contact

Skills

Core Skills

Physical DesignVlsi

Other Skills

FloorplanningEMIRClock Tree SynthesisStatic Timing AnalysisPlace & RoutePhysical VerificationSoCASICPower AnalysisLogic SynthesisFormal VerificationTCLPerlSedAwk

About

A VLSI Physical Design Engineer with exposure to Place and Route design methodologies, Physical Verification, IR drop analysis and Timing closure.

Experience

14 yrs 5 mos

Total Experience

2 yrs 6 mos

Average Tenure

3 yrs 6 mos

Current Experience

– Present

FloorplanningEMIRClock Tree SynthesisStatic Timing AnalysisPlace & RoutePhysical Verification+2

Broadcom

Principal Engineer

Dec 2022 – Present · 3 yrs 5 mos · Bengaluru, Karnataka, India · On-site

Qualcomm

Sr. Lead Engineer

Mar 2018 – Feb 2022 · 3 yrs 11 mos · Bengaluru, Karnataka, India

Intel india technology ltd

Sr Design Engineer

Jun 2016 – Feb 2018 · 1 yr 8 mos · Bangalore

Altran india

Design Engineer

Sep 2015 – Jun 2016 · 9 mos

Sicon design technologies pvt. ltd.

Physical Design Engineer

Apr 2011 – Aug 2015 · 4 yrs 4 mos · Bangalore

Eptech it solutions

Junior Engineer

Jan 2011 – Apr 2012 · 1 yr 3 mos · Hyderabad, Telangana, India

Education

Victoria University

Master in Micro-Electronic Engineering — VLSI

Jan 2004 – Jan 2006

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