MAHENDRAKUMAR G — Software Engineer

I am an ASIC Digital Design, Staff Engineer at Synopsys with 7.5 years of experience focusing on RTL Design, and Automations with a Master’s Degree in VLSI Design. Prior to joining Synopsys, I worked at Intel for 2.5 years , and I worked at AMD (Xilinx) for 5 years. I am working on RTL Design for High Speed Ethernet IP design. I worked on RTL Design for CXL2AXI protocol conversion bridge IP design. I worked on RTL Design for DDR memory PHY interface. I worked on RTL Design for Memories (Ultra-RAM and Block-RAM), Analog Mixed Signals and Custom Digital Circuits for next-generation FPGA products. I worked on Full Chip for Xilinx 7nm Versal products and Xilinx 16nm Zynq UltraScale+ products. I worked on Silicon testing of Memories and Custom Digital Circuits. I automated and enhanced many internal RTL/Circuit checks for different teams. I published IEEE papers on various optimization techniques and I worked on a design that was patented. I also got multiple recognition awards. I executed all of the tasks successfully including multiple tape-outs and helped multiple cross functional teams when help was needed by learning their designs.

Stackforce AI infers this person is a Semiconductor ASIC Design Engineer with extensive RTL design and automation expertise.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 5 mos