Sandip Gaikwad

Software Engineer

Bengaluru, Karnataka, India20 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in ASIC and Functional Verification
  • Led IP verification for DRAM and Audio IP
  • Extensive experience in SystemVerilog and UVM
Stackforce AI infers this person is a highly skilled ASIC and Functional Verification engineer in the semiconductor industry.

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Skills

Core Skills

Functional VerificationAsic

Other Skills

SVUVMperlpythonCAssemblyVHDLSoCVLSISystemVerilogRTL designVerilogNCSimTiming ClosureIntegrated Circuit Design

Experience

20 yrs 8 mos
Total Experience
2 yrs 2 mos
Average Tenure
1 yr 5 mos
Current Experience

Marvell technology

Principal Engineer

Jan 2025Present · 1 yr 5 mos · Bengaluru, Karnataka, India · On-site

  • Verification of Switch networking products. Subsystem and block level verification. Using SV, UVM, perl and python.
SVUVMperlpythonFunctional VerificationASIC

Intel corporation

Graphics Hardware Engineer at Intel

Oct 2020Apr 2025 · 4 yrs 6 mos · Bengaluru, Karnataka, India

Qualcomm

Staff Engineer

Mar 2016Oct 2020 · 4 yrs 7 mos · Bangalore

  • Audio IP verification using SV, UVM.
SVUVMFunctional Verification

Rambus

SMTS II Logic verification Engineer

Jul 2013Mar 2016 · 2 yrs 8 mos

  • Lead for IP verification, Using SV and UVM to verify DRAM IPs. Worked on DDR3/4 PHY verification, LPDDR2/3 PHY verification. Also worked in DRAM buffer chips.
  • Leading a team to execute projects.
SVUVMFunctional VerificationASIC

Zenverge

Staff Engineer

Mar 2012Jul 2013 · 1 yr 4 mos

  • 1. Verification of various IPs like PCIe, I2C, USB
  • 2. Block level verification of indigenous developed blocked for video processing.
  • 3. Using UVM, SV and C based testing
UVMSVCFunctional Verification

Mirafra technologies

Sr. Design Engineer

May 2011Mar 2012 · 10 mos · Bangalore

  • 1. Worked with Analog Devices. Microcontroller based SOC verification. Using system verilog and Assembly. Duration 4 months
  • 2. Client TI India. Graphics processor sub-system verification & USB 2.0 IP verification.
SVAssemblyFunctional Verification

Lsi technologies india pvt.ltd.

Design Engineer

Oct 2008May 2011 · 2 yrs 7 mos

  • Verification of Processors (PowerPC) and SOCs involving ARM processors.

Infineon technologies

Design Engineer I

Oct 2007Oct 2008 · 1 yr

  • Worked in Post SIlicon Validation of Wireless chipsets. Also involved in verification of wireless SOCs.

Agere systems

Design Engineer

Jan 2006Jan 2007 · 1 yr

  • 1. Post silicon validation of ARM based SOCs, wireless chipset.
  • 2. Involved writing of system level test cases for blocks like GPIO, I2C, Interrupt controller and USB.

Cmc ltd.(tata enterprise)

Design Engineer

Jan 2005Jan 2006 · 1 yr

  • 1. Implementing design on FPGA, for finger-print matching algorithm. Used VHDL for coding and synthesised the design using Xilinx tools.
VHDLASIC

Education

Indian Institute of Technology, Bombay

M.Tech — Microelectronics

Jan 2003Jan 2005

University of Mumbai

B.E — Instrumentation

Jan 2000Jan 2003

Vivekanand Education Society's Polytechnique

Diploma — Instrumentation

Jan 1997Jan 2000

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